Integrated circuits and methods of design and manufacture...

Details Integrated circuits and methods of design and manufacture... Integrated circuits and methods of design and manufacture...

2008-05-23

2011-10-18

Ngo, Ngan (Department: 2893)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S005000, C430S323000, C430S394000, C430S311000, C438S712000, C438S708000, C438S697000, C438S942000, C257SE21023

Reexamination Certificate

active

08039203

ABSTRACT:
Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

REFERENCES:
patent: 5308741 (1994-05-01), Kemp
patent: 5563012 (1996-10-01), Neisser
patent: 5821014 (1998-10-01), Chen et al.
patent: 6421820 (2002-07-01), Mansfield et al.
patent: 6734762 (2004-05-01), Cornett et al.
patent: 6777147 (2004-08-01), Fonseca et al.
patent: 6787469 (2004-09-01), Houston et al.
patent: 6929887 (2005-08-01), Lin et al.
patent: 7495294 (2009-02-01), Higashitani
patent: 2001/0020878 (2001-09-01), Speidell et al.
patent: 2004/0063038 (2004-04-01), Shin et al.
patent: 2006/0264001 (2006-11-01), Tran et al.
patent: 2008/0014684 (2008-01-01), Blatchford et al.
Meiring, J. E., et al., “ACLV Driven Double-Patterning Decomposition with Extensively Added Printing Assist Features (PrAFs),” Proceedings of SPIE, Conference Proceedings Paper, vol. 6520, Mar. 26, 2007, 12 pages.
Miller, S., et al., “Lithography Value Drivers in IC Design & Manufacturing,” Semiconductor Fabtech—30THEdition, Aug. 25, 2006, pp. 76-83.
Rabkin, P., et al., “Fabless/Foundry DFM: 45nm and Beyond,” Semiconductor Fabtech—32NDEdition, Dec. 20, 2006, pp. 76-82.
Haffner, H., et al., “Mastering Double Exposure Process Window Aware OPC by Means of Virtual Targets,” Proceedings of SPIE, Conference Proceedings Paper, vol. 6349, Oct. 20, 2006, 11 pages.

Affiliated with

Also associated with

Rating

Integrated circuits and methods of design and manufacture... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuits and methods of design and manufacture..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuits and methods of design and manufacture... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4291751