Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With electrical contact in hole in semiconductor
Reexamination Certificate
1999-12-17
2003-10-28
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With electrical contact in hole in semiconductor
C257S698000, C257S735000, C257S777000
Reexamination Certificate
active
06639303
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits, and more particularly to chip interconnection and to forming contact pads on the back side of a semiconductor chip, and also to thinning of integrated circuits after circuit elements have been fabricated.
Some techniques for forming contacts on the chip “second” side are disclosed in U.S. Pat. No. 5,270,261 issued Dec. 14, 1993 to Bertin et al. and entitled “Three Dimensional Multichip Package Methods of Fabrication”. Alternative techniques are desired.
SUMMARY
The invention provides methods for making back-side contact pads in a semiconductor die (or “chip”). The back-side contact pads are suitable for connecting the die to an underlying die to form a multi-die vertical integrated circuit. The invention also provides vertical integrated circuits. In addition, the invention provides methods for thinning of individual dice whether or not the dice will be part of a vertical integrated circuit.
In some embodiments of the present invention, back-side contact pads are formed as follows. A masked etch of the face side of a semiconductor wafer creates a via over each location where a back-side contact pad is to be formed. A dielectric is deposited over the via, and a conductive layer (for example, metal) is deposited over the dielectric. The bottom portion of the conductive layer in each via will form the back-side contact pad.
After the integrated circuit has been formed, the wafer is etched from the back side until the back-side contact pad is exposed. The etch etches the wafer substrate faster than it etches the dielectric separating the substrate from the pad. Therefore, the wafer substrate is receded relative to the dielectric so that the dielectric protrudes down relative to the substrate around each back-side contact pad. Thus the dielectric insulates the back-side contact pads from
In some embodiments, the protruding portion of the dielectric becomes gradually thinner around each contact pad when the dielectric is traced in the downward direction away from the substrate.
In some embodiments, the protruding portion of the dielectric becomes gradually thinner around each contact pad when the dielectric is traced in the downward direction away from the substrate.
In some embodiments, the wafer is held by a non-contact wafer holder during the back-side etch. The face side of the wafer does not physically contact the holder. Therefore, there is no need to cover the face side with any protective layer to protect the wafer during the etch. Further, the holder protects the face side circuitry from the etch.
The wafer is diced into dice before or after the back-side etch.
In some embodiments, the back-side contact pads are used for vertical integration.
In some embodiments, the dice are not used for vertical integration. The dice are thinned to reduce their vertical dimension.
Other embodiments and variations are within the scope of the invention.
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Shenker Micheal
Skjerven Morrill LLP
Thomas Tom
Tru-Si Technolgies, Inc.
Vu Hung Kim
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