Integrated circuits

Details Integrated circuits Integrated circuits

1999-08-20

2001-09-18

Smith, Matthew S (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S348000, C438S222000, C438S223000, C438S298000

Reexamination Certificate

active

06291859

ABSTRACT:

The present invention relates to integrated circuits, and in particular, but not exclusively, to noise sensitive, mixed signal circuits.
DESCRIPTION OF THE RELATED ART
A recent trend in the design of digital radio for mobile telephony is to combine as many functions as possible on a single monolithic integrated circuit IC. For example, digital circuitry, and analogue-to-digital (A/D) and digital-to-analogue (D/A) converters are usually implemented in CMOS technology. The analogue radio frequency (RF) circuitry can also be implemented in CMOS technology, which can lead to integration of such circuits. For example, see S. Sheng et al. “A Low-Power CMOS Chipset for Spread-Spectrum Communications”, International Solid-State Circuits Conference, 1996.
The demand for higher levels of integration leads to the implementation of high-resolution analogue circuits on the same substrate as large digital VLSI systems. However, in such mixed-signal systems, the coupling of digital switching noise into sensitive analogue circuits can significantly limit the performance that can be achieved in analogue signal processing and data conversion circuits. The noise coupling generally occurs through the silicon substrate of the integrated circuit. For example, see R. B. Merrill, W. M. Young, K. Brehmer “Effect of Substrate Material on Crosstalk in Mixed Analog/Digital Integrated Circuits” IEDM Tech. Dig. 1994, pp. 433-436.
A typical CMOS integrated circuit design is shown in
FIGS. 1 and 2
.
FIG. 1
shows a PMOS transistor, and
FIG. 2
shows an NMOS transistor. The integrated circuit are formed on a substrate
1
of p+ type semiconductor material. The substrate
1
carries an epitaxial layer
2
of p type semiconductor material, in which there is formed a well
3
,
3
′ of material. In the case of a PMOS transistor (FIG.
1
), the well
3
is of n type material, and in the case of an NMOS transistor (FIG.
2
), the well is of p type material. As is well known, the transistor structure is formed by providing source and drain areas
4
,
4
′,
5
,
5
′ within the well
3
,
3
′ and a gate region
6
above the well
3
,
3
′. The PMOS transistor has source and drain areas
4
,
5
of p+ type material, and the NMOS transistor has source and drain areas
4
′,
5
′ of n+ type material.
An implant region
7
is provided which serves to control the threshold voltage (Vth) of the transistor. The threshold voltage is set by the charge content of the implant region
7
.
With the design of CMOS integrated circuit shown in
FIGS. 1 and 2
, digital switching noise from digital circuits located on the same substrate as analogue circuits can easily disturb those analogue circuits.
The addition of pn-junctions to isolate the NMOS transistors from the substrate can improve the noise rejection characteristics of combined circuits. For example an extra deep n-type well can be used to surround the p-type well of an NMOS transistor. For example, U.S. Pat. No. 5,323,043 improves the noise isolation by introducing junction capacitances between the transistors and the substrate.
However, such solutions require the use of an additional diffused layer or well of material, which can increase the cost of the integrated circuit.
SUMMARY OF THE PRESENT INVENTION
According to a first aspect of the present invention there is provided a semiconductor integrated circuit comprising a substrate of a first conduction type semiconductor material, an epitaxial layer which is carried by the substrate and which is of a second conduction type semiconductor material different to the first conduction type material, a well of semiconductor material in the epitaxial layer and a semiconductor device formed in and/or on said well of semiconductor material, wherein the epitaxial layer is substantially depleted of charges in a region substantially beneath the well when the circuit is subjected to a bias voltage.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit comprising:
providing a substrate of first conduction type semiconductor material;
forming an epitaxial layer of semiconductor material on the substrate;
forming a well of semiconductor material in the epitaxial layer; and
forming a semiconductor device structure in and/or on the well of the material,
wherein the epitaxial layer is of a second conduction type semiconductor material, the second conduction type being different to the first conduction type, and wherein the epitaxial layer is formed so as to be substantially depleted of charges in a region substantially beneath the well when the circuit is subjected to a bias voltage.


REFERENCES:
patent: 4595941 (1986-06-01), Avery
patent: 4698653 (1987-10-01), Cardwell, Jr.
patent: 5319236 (1994-06-01), Fujihira
patent: 5323043 (1994-06-01), Kimura et al.
patent: 5726475 (1998-03-01), Sawada
patent: 0 422 250 (1991-04-01), None
patent: 0 817 268 (1998-01-01), None
Patent Abstracts of Japan vol. 012, No. 330 (E-655), Sep. 1988—& JP 63 094667A (Fuji Electric Co. Ltd.), Apr. 1988, Abstract; Fig. 5.

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