Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1998-11-04
1999-11-09
Everhart, Caridad
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438978, 438703, H01L 2144
Patent
active
059813970
ABSTRACT:
A method of forming integrated circuitry includes, a) providing a pair of spaced and adjacent electrically conductive elongated lines; and b) providing electrically insulative material over the pair of spaced lines in a manner which leaves an elongated void between the lines, the elongated void being top sealed along its substantial elongated length. Preferably, the electrically insulative material is provided by depositing electrically insulative material over the pair of lines in a manner which produces a retrograde cross-sectional profile of the insulating material relative to the respective line sidewalls and which leaves an elongated top sealed void within the insulating material between the lines, the elongated void being open at at least one end. The void at the one end is subsequently sealed. Integrated circuitry of the invention included, i) a pair of spaced and adjacent electrically conductive elongated lines; and ii) the pair of conductive lines being encapsulated with an electrically insulative material, a top sealed elongated void provided relative to the electrically insulative material between the lines facilitating electrical isolation of the lines from one another.
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Everhart Caridad
Micro)n Technology, Inc.
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