Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-04-24
2001-07-24
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S132000, C438S601000, C438S625000, C257S529000, C257S665000
Reexamination Certificate
active
06265299
ABSTRACT:
TECHNICAL FIELD
This invention relates to integrated circuitry fuse forming methods, integrated circuitry programming methods, and integrated circuitry comprising programmable integrated circuitry.
BACKGROUND OF THE INVENTION
Some types of integrated circuitry utilize fuses. A fuse is a structure which can be broken down or blown in accordance with a suitable electrical current which is provided through the fuse to provide an open circuit condition. Within the context of integrated circuitry memory devices, fuses can be used to program in redundant rows of memory. Fuses have use in other integrated circuitry applications as well.
One problem associated with integrated circuitry fuses is that the voltage required to provide the necessary current to blow the fuse can be very high, e.g., on the order of 10 volts. Because of this, memory circuitry utilizing MOS logic cannot typically be used to route an appropriate programming signal or current to the fuse since the voltage required to do so would break down the gate oxide of the MOS device. One solution has been to provide a dedicated contact pad for each fuse so that the desired programming voltage can be applied directly to the fuse from an external source without the use of the MOS devices. Providing a dedicated contact pad, however, utilizes valuable silicon real estate which could desirably be used for supporting other memory devices.
This invention arose out of concerns associated with providing improved integrated circuitry fuse forming methods and resultant fuse constructions suitable for programming at relatively low programming voltages. This invention also arose out of concerns associated with conserving wafer real estate and providing integrated circuitry which incorporates such improved fuse constructions.
SUMMARY OF THE INVENTION
Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided. The programming circuitry comprises at least one MOS device which is capable of being utilized to provide a programming voltage which is sufficient to blow the fuse, and which is no greater than the breakdown voltage of the one MOS device.
REFERENCES:
patent: 3647585 (1972-03-01), Fritzinger et al.
patent: 4032949 (1977-06-01), Bierig
patent: 4198744 (1980-04-01), Nicolay
patent: 4460914 (1984-07-01), te Velde et al.
patent: 4517583 (1985-05-01), Uchica
patent: 4757359 (1988-07-01), Chiao et al.
patent: 4782380 (1988-11-01), Shankar et al.
patent: 4814853 (1989-03-01), Uchida
patent: 4847732 (1989-07-01), Stopper et al.
patent: 4935801 (1990-06-01), McClure et al.
patent: 4984054 (1991-01-01), Yamada et al.
patent: 4998223 (1991-03-01), Akaogi
patent: 5015604 (1991-05-01), Lim et al.
patent: 5070392 (1991-12-01), Coffey et al.
patent: 5155462 (1992-10-01), Morrill, Jr.
patent: 5244836 (1993-09-01), Lim
patent: 5291434 (1994-03-01), Kowalski
patent: 5376820 (1994-12-01), Crafts et al.
patent: 5485031 (1996-01-01), Zhang et al.
patent: 5614440 (1997-03-01), Bezama et al.
patent: 5661323 (1997-08-01), Choi et al.
patent: 5756393 (1998-05-01), Dennison
patent: 5903041 (1999-05-01), La Fleur et al.
patent: 5914524 (1999-06-01), Komenaka
patent: 5949127 (1999-09-01), Lien et al.
patent: 5976917 (1999-11-01), Manning
patent: 6060398 (2000-05-01), Brintzinger et al.
patent: 6080649 (2000-06-01), Werner et al.
Bowers Charles
Micro)n Technology, Inc.
Sarkar Asok K.
Wells, St. John, Roberts, Gregory & Matkin PS
LandOfFree
Integrated circuitry fuse forming methods, integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuitry fuse forming methods, integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuitry fuse forming methods, integrated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2559873