Integrated circuitry for checking the utilization rate of redund

Details Integrated circuitry for checking the utilization rate of redund Integrated circuitry for checking the utilization rate of redund

1994-12-07

1996-02-20

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 36523006, G11C 700, G11C 2900

Patent

active

054935318

ABSTRACT:
An integrated circuit for checking the utilization rate of redundancy memory elements in semiconductor memory device, comprising a matrix of memory elements and a redundancy circuitry which comprises a plurality of programmable non-volatile memory registers, each supplied with address signals to generate a redundancy selection signal for the selection of an associated redundancy memory element when the address signals coincide with the address stored therein, and combinatorial circuit means supplying the non-volatile memory registers with an inhibition signal for inhibiting the generation of the respective redundancy selection signals when the address signals coincide with the address stored in a non-programmed non-volatile memory register; the integrated circuitry comprises multiplexing circuit means, controlled by a control signal generated by a control circuitry of the memory device, for transmitting the redundancy selection signals to output pads of the memory device when the control signal is activated; the control signal is also supplied to said combinatorial circuit means to prevent when activated the generation of said inhibition signal.

REFERENCES:
patent: 4586170 (1986-04-01), O'Toole et al.
patent: 5124949 (1992-06-01), Morigami

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