Integrated circuit with uniform polysilicon perimeter...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

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07849433

ABSTRACT:
Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.

REFERENCES:
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patent: 6938226 (2005-08-01), Nguyen et al.
patent: 7089520 (2006-08-01), Voldman
patent: 7095063 (2006-08-01), Cohn et al.
patent: 2007/0118320 (2007-05-01), Luo et al.
Kahng, et al., “Filling Algorithms and Analyses for Layout Density Control,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, No. 4, Apr. 1999, pp. 445-462.
Kahng, A., “IC Layout and Manufacturability: Critical Links and Design Flow Implications,” UCLA Department of Computer Science, pp. 1-6.

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