Integrated circuit with unified memory system and dual bus...

Details Integrated circuit with unified memory system and dual bus... Integrated circuit with unified memory system and dual bus...

1998-10-05

2001-06-12

Dharia, Rupal D. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S100000, C710S240000, C711S147000, C711S149000, C711S150000

Reexamination Certificate

active

06247084

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits and, in particular, to an integrated circuit having a unified memory architecture.
Unified memory architectures have been used for various computer applications, such as network computers, Internet appliances and mission specific terminal applications. In a typical unified memory architecture, all devices requiring access to memory are coupled to a common system bus. These devices can include a processor, an input-output device or a graphics device, for example. A memory controller arbitrates access to memory between the various devices.
Memory latency is a common difficulty in unified memory architectures since each device must arbitrate for access to memory over the system bus. Latency can be reduced by requesting bursts of data from memory. For example, graphics devices may request bursts of display data from a frame buffer. Since graphics devices continually supply data to a screen display, these devices have a high bandwidth requirement and cannot easily accommodate long memory latencies. On the other hand, processors typically request specific data from memory or another device and then wait for the data without giving up access to the system bus. Also, processors require a relatively high priority. This often results in contention for the system bus between the processor and devices having high bandwidth requirements.
A conventional system with multiple bus masters uses an address bus and a data bus to control the memory system. Typically, both of these busses are arbitrated for and granted to one master at a time. Many cycles of bus time are lost due to dead time between masters, and time required for each master to communicate its data request to the memory controller. In addition, the processor uses the same bus for doing “program Input/Output” functions, which are very inefficient in terms of bus utilization.
A typical system that includes a raster scan display output for graphics uses a second memory system for this time critical function. Not only does this extra memory system increases cost, but the overall performance of the system is impacted due to the need for the data to be copied from processor memory space into the display memory space.
SUMMARY OF THE INVENTION
The unified memory system of the present invention provides a high enough bandwidth to enable a graphics and display subsystem to use the same memory as a processor and other bus transactor circuits. The unified memory system includes a processor, a memory controller, a plurality of bus transactor circuits and a shared memory port. A processor bus is coupled between the processor and the memory controller. A first multiple-bit, bidirectional system bus is coupled between the shared memory port, the memory controller and the plurality of bus transactor circuits. A second multiple-bit, bidirectional system bus is coupled between the memory controller and the plurality of bus transactor circuits.
Another aspect of the present invention relates to a method of passing data between a shared memory port, a memory controller and a plurality of bus transactor circuits, the method includes: passing memory data between the shared memory port, the memory controller and the plurality of bus transactor circuits over a multiple-bit, bidirectional data bus; passing non-memory data between the memory controller and the plurality of bus transactor circuits over a multiple-bit, bidirectional command bus; controlling access by the plurality of bus transactor circuits to the data bus with the memory controller; and controlling access by the plurality of bus transactor circuits to the command bus with the memory controller independently of access to the data bus.


REFERENCES:
patent: 5561777 (1996-10-01), Kao et al.
patent: 5805905 (1998-09-01), Biswas et al.
patent: 5822768 (1998-10-01), Shakkarwar
patent: 5854638 (1998-12-01), Tung

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