Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-26
2002-03-12
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S631000, C438S634000, C438S637000, C438S638000
Reexamination Certificate
active
06355552
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 98-06687, filed May 27, 1998, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to semiconductor integrated circuits having a stack of conducting layers separated by insulating layers.
2. Description of Related Art
In conventional integrated circuits, electrical connections must be made between conducting metallized layers that are on different levels and separated by one more insulating layers. In a conventional manufacturing process, two conducting layers are electrically connected through vias, which are holes in the insulating layer that are filled with metal. In order to reduce the width of the metal lines of a conducting metallized layer, lines having a width equal to the width of the vias are used.
This type of integrated circuit can be produced using the “Damascene” process in which a first insulating layer is deposited on a metallization layer of level n and holes are etched through the insulating layer. The metal for the via is then deposited and polished until it is level with the upper surface of the insulating layer, and then a new insulating layer is deposited on the formed via of level n. The trenches for the lines are etched, metal for the lines of the metallization layer is deposited and then polished until it is level with the upper surface of the insulating layer, and so on. A via normally has to be precisely positioned on a line, and a line of the subsequent metallization level normally has to be precisely positioned on the via.
However, due to the alignment tolerances of the machines for photoetching the holes and trenches in which the vias and lines are formed, an offset can occur (e.g., of about one-third of the width of a hole or trench). Thus, when etching an insulating layer, the existing via or line in the lower insulating layer does not form an etching stop barrier over the entire surface of the trench or hole during the etching process. As a result, the etching can be carried out in the lower layer on one side of the via or line without any accurate control of the depth of the hole in the lower insulating layer. When the hole in the upper layer is then filled with metal, the contact area between the via and line is not accurately known and thus the electrical resistance between these two elements is not easily known. With respect to the lines, the depth of the trenches cannot be reproducibly controlled so there is a spread in line resistances.
There is another conventional process differing slightly from the one described above that seeks to control the depth of the trenches by avoiding lateral contact between vias and lines of different levels. In this process, a “stop layer” is placed on the lower insulating layer. The holes in the stop layer and in the lower insulating layer are etched, the holes are filled with metal and polished, and then an upper insulating layer and an upper stop layer are deposited. The hole in the upper insulating layer is etched using a process that is incapable of etching the lower stop layer so the etching stops on the upper surface of the stop layer.
The etching is begun using a process that is capable of etching each stop layer. Because the thickness of the stop layers is relatively small compared with the associated insulating layers, it is possible to interrupt the etching before the entire thickness of the associated insulating layer has been etched. The etching is selectively stopped with respect to the stop layer and the associated metallization level. Thus, the hole in the upper insulating layer is bounded by the upper surface of the lower stop layer and the metallization level or associated vias. As a result, the etching depth of a hole or trench is controlled satisfactorily, even when there is an offset between the vias and the lines of two adjacent layers. However, when there is such an offset, the contact area between a via and a line in superposition can be lessened so as to cause an increase in the electrical resistance between these two elements.
SUMMARY OF THE INVENTION
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a process that makes it possible to both control the etching depth and obtain contact areas that are sufficiently large and relatively constant. In the process, a second dielectric layer is formed above a first dielectric layer, and holes and/or trenches are etched in the first and second dielectric layers. The holes and/or trenches are filled with metal in order to form electrical connection elements, and at least a third dielectric layer is formed. Holes and/or trenches are selectively etched in the third dielectric layer and the second dielectric layer with respect to the first dielectric layer and the elements, in order to control the depth of the etch. If there is an offset between vias or lines in superposition, a lateral contact between these two elements can be made within the thickness of the dielectric layer placed under the third dielectric layer while at the same time controlling the depth of the trenches (or of the elements in general). Thus, it is possible to keep the contact area between these two elements substantially constant so as to improve the integrated circuit by taking advantage of a characteristic that constituted a defect in conventional circuits.
Another object of the present invention is to provide an integrated circuit having substantially constant electrical resistance between superposed vias. The integrated circuit is of the type having metallization levels separated by dielectric layers and metallized vias connecting lines of different metallization levels. Additionally, the integrated circuit includes first and second metallization levels, first and second superposed dielectric layers located above the first metallization level, and a third dielectric layer located above the first and second dielectric layers. At least one electrical connection element is provided in the third dielectric layer and passes through the second dielectric layer until it comes into contact with the first dielectric layer. Because the metallized elements have a lateral surface adjacent to their upper surface, at least one element, via, or line includes a portion level with the adjacent dielectric layer below the third layer, in contact with the lateral surface of the corresponding element provided in the two layers. Thus, the thickness of the lines and their electrical resistance are satisfactorily controlled.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.
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Gayet Philippe
Granger Eric
Bongini Stephen
Fleit Kain Gibbons Gutman & Bongini P.L.
Gurley Lynne A.
Niebling John F.
STMicroelectronics S.A.
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