Integrated circuit with self-biased differential data lines

Details Integrated circuit with self-biased differential data lines Integrated circuit with self-biased differential data lines

1991-12-17

1993-10-26

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36523006, G11C 0000

Patent

active

052572269

ABSTRACT:
An integrated circuit, such as a memory, having an internal data bus and circuitry for precharging the same, with each data conductor in the said data bus associated with a dummy data conductor, which is driven to a complementary logic state from that of its associated data conductor. During precharge and equilibration at the beginning of a cycle, initiated by an address transition detection or by a clock signal, each data conductor is connected to its dummy data conductor so that the data conductor is precharged to a midlevel by way of charge sharing. Also during precharge and equilibration, the data driver is placed in a high impedance state by the sense amplifier output nodes both going to the same logic level. This midlevel precharge allows for faster switching, and reduced instantaneous current, than obtained for rail-to-rail switching. Self-biasing circuits are connected to each of the data conductors and dummy data conductors, to prevent floating conditions during long precharge and equilibration periods. The output stage receiving the data conductor is preferably disabled during precharge and equilibration, so that the data conductor can be precharged near the trip level of the output stage, without risking output stage oscillations. A termination is also provided for the dummy data conductor, matching the load presented by the output stage to the data conductor, so that the data conductor and its dummy data conductor are at complementary states even during transient conditions.

REFERENCES:
patent: 4394748 (1983-07-01), Campbell
patent: 4494219 (1985-01-01), Tanaka
patent: 4813020 (1989-03-01), Iwamura
patent: 4817055 (1989-03-01), Arakawa
patent: 4961170 (1990-10-01), Fujitsu
patent: 4992677 (1991-02-01), Ishibashi
patent: 5062082 (1991-10-01), Choi
patent: 5109187 (1992-04-01), Guliani
patent: 5146427 (1992-09-01), Sasaki

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