Integrated circuit with selectively disabled logic blocks

Details Integrated circuit with selectively disabled logic blocks Integrated circuit with selectively disabled logic blocks

1999-01-14

2000-12-12

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 41, H03K 19177

Patent

active

061604186

ABSTRACT:
A method and circuit is provided for creating multiple product lines from a single silicon implementation of an integrated circuit (IC). Specifically, logic blocks within the IC are selectively disabled after manufacturing the IC to create various ICs of different functionality from a single silicon implementation of the IC. In one embodiment, a first logic block of the IC is coupled to a disable circuit by a first disable line and a second logic block of the IC is coupled to the disable circuit by a second disable line. The disable circuit can disable the first logic block by driving the first disable line to a disable logic state. Similarly, the disable circuit can disable the second logic block by driving the second disable circuit to the disable logic state. In an FPGA embodiment of the present invention, the first logic block is a row of configurable logic blocks (CLBs) and the second logic block is a column of CLBs.

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