Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-25
2007-12-25
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
11099772
ABSTRACT:
An integrated circuit layout is provided, which includes a base platform for an integrated circuit, a processor hardmac and a support memory. The base platform includes a memory matrix having leaf cells arranged in rows and columns. Each column of leaf cells has interface pins that are routed to a common matrix edge and have a common pin order along the matrix edge. The processor hardmac is placed along the memory matrix and has a hardmac edge adjacent the memory matrix edge and a plurality of interface pins for interfacing with corresponding interface pins of the memory matrix. The interface pins of the processor hardmac have the same pin order along the hardmac edge as the interface pins along the matrix edge. The support memory for the processor hardmac is mapped to a portion of the memory matrix along the hardmac edge.
REFERENCES:
patent: 6593772 (2003-07-01), Ngai et al.
patent: 6804811 (2004-10-01), Andreev et al.
patent: 7036102 (2006-04-01), Andreev et al.
patent: 7111264 (2006-09-01), Andreev et al.
patent: 7168052 (2007-01-01), Andreev et al.
patent: 7219321 (2007-05-01), Nikitin et al.
patent: 2005/0108495 (2005-05-01), McKenney et al.
U.S. Appl. No. 10/713,492, filed Nov. 14, 2003, Flexible Design for Memory of Integrated Circuits (38 pages).
U.S. Appl. No. 10/875,128, filed Jun. 23, 2004, Yield Driven Memory Placement System (33 pages).
U.S. Appl. No. 10/688,460, filed Oct. 17, 2003, Process and Apparatus for Fast Assignment of Objects to a Rectangle (22 pages).
U.S. Appl. No. 10/694,208, filed Oct. 27, 2003, Process and Apparatus for Placement of Cells in an IC During Floorplan Creation (26 pages).
U.S. Appl. No. 10/830,739, filed Apr. 23, 2004, Process and Apparatus for Memory Mapping (26 pages).
U.S. Appl. No. 10/713,492, filed Nov. 14, 2003, Flexible Design for Memory Use in Integrated Circuits (51 pages).
Casey Michael J.
McKernan Thomas W.
Vogel Danny C.
Garbowski Leigh M.
LSI Corporation
Westman Champlin & Kelly P.A.
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