Integrated circuit with reduced clock skew

Details Integrated circuit with reduced clock skew Integrated circuit with reduced clock skew

1994-06-01

1996-03-05

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326101, 327293, H03K 1902, H01L 2500

Patent

active

054971098

ABSTRACT:
Integrated circuits in which a phase difference between the external and internal clocks can be reduced by decreasing transistor stages from the input of an external clock to the output of an internal clock drive stages and also noise can be reduced which is generated when the clock driver drives at a high speed the internal clock having a heavy load and the noise can be prevented from propagation to other portions to avoid having a bad effect on other circuits, and further the internal clock having the same phase can be supplied to each part of the chip even at a high operating frequency by minimizing skew of the internal clock signal on the chip and still further a demand current can be reduced by eliminating a passing current of the internal clock signal driver.

REFERENCES:
patent: 4958092 (1990-09-01), Tanaka
patent: 5122693 (1992-06-01), Honda
patent: 5278466 (1994-01-01), Honoa
patent: 5376842 (1994-12-01), Honoa

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