Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-10-23
2007-10-23
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C327S108000
Reexamination Certificate
active
11047161
ABSTRACT:
An impedance matching between two integrated circuits is achieved using an impedance measuring circuit in the integrated circuit that contains an impedance-programmable output buffer (IPOB) that is to have its output impedance changed. The impedance measuring device is directly connected to the output of the IPOB so that it is detecting the same impedance that the IPOB will drive and thereby avoids the errors of measuring the resistance of a device that imperfectly models the actual impedance. The impedance measuring device is preferably an analog to digital (A/D) converter that provides a digital output relative to the voltage present on the same terminal as the output of the IPOB. By having the A/D converter on the same integrated circuit as the IPOB, communications difficulties between the A/D converter and the IPOB are minimal.
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JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79, Release 2, May 2002, pp. 1-79, no date.
JESD79-2, DDR2 SDRAM Specification, Mar. 2003, pp. 1-79, no date.
Clingan, Jr. James L.
Freescale Semiconductor Inc.
Tan Vibol
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