Integrated circuit with programmable bus configuration

Details Integrated circuit with programmable bus configuration Integrated circuit with programmable bus configuration

1995-11-20

1999-06-01

Sheikh, Ayaz R.

395828, 395830, G06F 1300

Patent

active

059095571

ABSTRACT:
A technique for configuring a processor allows the processor to interface with external buses of different types; for example, busses having different data widths. Configuration data is stored in a memory, typically a read-only memory, and transferred to the processor during a system configuration period. An initial configuration fetch may be accomplished to retrieve the configuration information prior to executing an actual processor instruction. Alternatively, the configuration information may be included in an actual instruction word. The system configuration period typically occurs during the initial power-on sequence, but may occur at other times.

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"H8/3042 Series Hardware Mannal", published by Semiconductor and IC Div. Hitachi, Ltd., 1st Edition, Feb. 1994, pp. 6, & 55-61. Figure 1-2 shows dedicated mode pins MD.sub.0, MD.sub.1, MD.sub.2. These pins are discussed on p. 55 for accessing data busses of either 8 or 16 bits width.
"M68HC11 Reference Manual", published by Motorola, Inc., Rev. 3, 1991, pp. 2-9--2-11 & 2-33--2-34.

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