Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Non-single crystal – or recrystallized – active junction...
Patent
1993-05-24
1995-04-25
Limanek, Robert P.
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Non-single crystal, or recrystallized, active junction...
257513, 257514, H01L 21324, H01L 21316, H01L 21477
Patent
active
054101760
ABSTRACT:
A method for forming isolation structures in an integrated circuit, and the structures so formed, are disclosed. After definition of active regions of the surface is accomplished by provision of masking layers, recesses are etched into the exposed locations, to a depth on the order of the final thickness of the insulating isolation structure. Sidewall spacers of silicon dioxide, or another insulating amorphous material, are disposed along the sidewalls of the recesses, with silicon at the bottom of the recesses exposed. Selective epitaxial growth of silicon then forms a layer of silicon within the recesses, preferably to a thickness on the order of half of the depth of the recess. The epitaxial silicon is thermally oxidized, filling the recesses with thermal silicon dioxide, having a top surface which is substantially coplanar with the active regions of the surface. According to an alternative embodiment, the formation of the sidewall spacers may be done in such a manner that narrower recesses remain filled with the material of the sidewall spacers.
REFERENCES:
patent: 4211582 (1980-07-01), Horng et al.
patent: 4661202 (1987-04-01), Ochii
patent: 4740480 (1988-04-01), Ooka
patent: 4842675 (1989-06-01), Chapman et al.
patent: 4958213 (1990-09-01), Eklund et al.
patent: 5073813 (1991-12-01), Morita et al.
Chen Fusen E.
Liou Fu-Tai
Anderson Rodney M.
Fahmy Wael M.
Jorgenson Lisa K.
Limanek Robert P.
Robinson Richard K.
LandOfFree
Integrated circuit with planarized shallow trench isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit with planarized shallow trench isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit with planarized shallow trench isolation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1569667