Integrated circuit with planar dielectric layer

Details Integrated circuit with planar dielectric layer Integrated circuit with planar dielectric layer

1991-11-15

1993-04-06

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437228, 437238, 437240, 437186, 437978, H01L 2144

Patent

active

052003582

ABSTRACT:
Self-aligned contacts are formed to regions between closely spaced features by a method which uses differential etch rates between first and second dielectrics deposited over the closely spaced features.

REFERENCES:
patent: 5037777 (1991-08-01), Mele et al.
patent: 5069747 (1991-12-01), Cathey et al.

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