Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-03-17
2003-02-18
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S147000, C711S154000, C713S152000, C710S200000
Reexamination Certificate
active
06523099
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit housing a memory therein, and particularly to an integrated circuit including an access port made according to predetermined standards.
2. Description of the Related Art
Heretofore, there have been developed and manufactured a variety of integrated circuits housing microprocessors (e.g. CPU (central processing unit), DSP (digital signal processor), etc.) or memories in addition to a logic section. Debugging is indispensable for such integrated circuits in order to inspect an error in software and to correct such error, if any, when software executed by a microprocessor is, developed In order to effect such debugging, it is customary that software stored in the memory incorporated within the integrated circuit is read out and checked.
In order to execute such debugging, there is standardized a protocol by which software can be comparatively easily read out from the memory housed within the integrated circuit. There has been developed an integrated circuit including an access port made according to JTAG (joint test action group) standards standardized in IEEE1149.1 standards and in which information within the integrated circuit can be exchanged between it and the outside by using a protocol (hereinafter referred to as JTAG protocol) standardized by the JTAG standards.
FIG. 1
is a schematic block diagram showing an example of such integrated circuit. As shown in
FIG. 1
, an integrated circuit
10
includes a microprocessor
11
. As circuits for processing data under control of this microprocessor
11
, the integrated circuit
10
includes a ROM (read-only memory)
12
for storing program data as software, a RAM (random-access memory)
13
for temporarily storing data upon processing and a logic unit
14
for executing processing. A bus line
15
is connected to the ROM
12
, the RAM
13
, the logic unit
14
and the microprocessor
11
. The integrated circuit
10
includes a data input and output (I/O) port
16
from which data processed by the integrated circuit
10
is outputted or through which data is inputted to the integrated circuit
10
. An external memory (e.g. external ROM, external RAM, etc.)
20
connected to this data I/O port
16
becomes able to transfer data among it and respective units within the integrated circuit
10
through the bus line
15
.
When the integrated circuit is of an integrated circuit conforming to the above-mentioned JTAG standards, this type of integrated circuit includes an access port
17
standardized by the JTAG standards independently of the data I/O port
16
. A device connected to the access port
17
in order to effect debugging and the microprocessor
11
become able to transfer data through a JTAG interface (I/F) circuit
18
. The access port
17
standardized by the JTAG standards includes, at minimum, four ports (test clock signal port: TCK, test mode select signal port; TMS, test reset signal port: TRST, test data input signal port: TDI) and one output port (test data output signal port: TDO). Information is transmitted and received between the JTAG I/F circuit
18
and the microprocessor
11
via a JTAG protocol control signal. Although not shown, the microprocessor
11
incorporates therein a section capable of interpreting the JTAG protocol control signal.
In the case of the integrated circuit thus arranged, by supplying the JTAG protocol control signal, which is used to read data from the ROM
12
, to the access port
17
from the outside, all data can be read out from the ROM
12
to devices connected to the I/O port
16
, thereby making it easy to debug software built in the integrated circuit.
However, if data had been read out from the memory housed within the integrated circuit by the protocol control signal such as the JTAG protocol control signal, scrambled data such as unintelligible data would be easily outputted to the outside. It is not preferable that a program, used to encrypt communication data, should easily read out from an integrated circuit for communication processing, for example. In particular, in the case of the standardized protocol such as JTAG protocol, since its control program also is made open to the public, and a debugging tool of built-in software also is made open to the public, those who do not have sophisticated knowledge of software are able to read, out data from the memory provided within the integrated circuit. This is not preferable from a secrecy standpoint.
SUMMARY OF THE INVENTION
In view of the aforesaid aspect, it is an object of the present invention to provide an integrated circuit in which data can be read out to the outside by a predetermined protocol and in which reading of data that should be made unintelligible can be limited.
According to an aspect of the present invention, there is provided an integrated circuit in which data can be read out from a memory. This integrated circuit comprises an access detecting circuit for detecting whether or not an access using an access port is made and an output inhibit circuit for inhibiting the output of data stored in a memory. Even when control data instructing the reading of data from the memory by using the access port is supplied from the outside, with respect to predetermined data on which an inhibit processing is effected by the output inhibit circuit, its output processing is inhibited and the data is not outputted to the outside.
REFERENCES:
patent: 4821177 (1989-04-01), Koegel et al.
patent: 5251304 (1993-10-01), Sibigtroth et al.
patent: 5465341 (1995-11-01), Doi et al.
patent: 5737760 (1998-04-01), Grimmer, Jr. et al.
patent: 5784577 (1998-07-01), Jacobsen et al.
Chace C. P.
Kim Matthew
Maioli Jay H.
Sony Corporation
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