Integrated circuit with non-binary decoding and data access

Details Integrated circuit with non-binary decoding and data access Integrated circuit with non-binary decoding and data access

1997-01-31

1998-12-29

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36518901, G11C 1300

Patent

active

058547630

ABSTRACT:
This invention describes an addressing and data access method and apparatus which can make use of maximum sized, binary configured blocks of memory or macro cells. The binary sized blocks of memory may be used to implement a non-binary sized overall memory circuit. The apparatus as described makes efficient use of silicon area by combining an optimized number of memory blocks or macro cells having at least two data port per macro cell to implement a non-binary sized memory circuit.

REFERENCES:
patent: 5093805 (1992-03-01), Singh
patent: 5315558 (1994-05-01), Hag
patent: 5349552 (1994-09-01), Zampagliane
patent: 5522059 (1996-05-01), Marushima et al.
patent: 5541850 (1996-07-01), Vander Zanden

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