Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-08-29
2004-05-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S689000, C438S692000, C438S584000, C438S595000
Reexamination Certificate
active
06737346
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to design layout for metal layers of an integrated circuit, and more specifically to modifying the spacing between metal features that are diagonally-adjacent to one another, in order to better planarize the topology of a subsequently deposited dielectric layer over the metal features.
BACKGROUND
Conventionally designed metal line layouts of integrated circuits (IC) structures can result in large spaces between nearest parallel, electrically isolated metal lines. These spacings arc random in size and have a great variety of dimensions. When an intermetal dielectric layer (IDL), such as an oxide, is deposited over the metal lines having random spacing between them, the top surface of the IDL will have a highest altitude equal to the thickness of the metal features (T
met
) plus the thickness of the IDL (T
IDL
) In those areas where there are no metal features but only open space, the altitude of the top surface of the IDL will be T
IDL
.
FIG. 1
illustrates a side, cross-sectional view of a conventional integrated circuit structure, which includes a series of metal features
102
and an IDL
104
situated on a substrate
106
. For example purposes, each metal line has a thickness, T
met
110
, and a width, W
met
112
. The thickness of IDL, T
IDL
, is indicated at
114
. The highest altitude of the top surface of IDL
104
is T
met
+T
IDL
, as indicated at
116
.
FIG. 1
shows IDL
104
as being non-planarized and having both wide
132
and narrow trenches
130
in the top surface of IDL
104
. Where the spacing between two metal features is small, a narrow trench
130
results. Where the spacing between metal features is larger, a wider trench
132
results.
FIG. 1
also shows that the surface of IDL
104
is constant in large areas where no metal features exist, such as the right-hand side of
FIG. 1
, showing the top surface of IDL
104
to have an altitude of T
IDL
, as indicated at
134
. Accordingly, the prior art methods result in a nonplanar structure with heights of the IDL that vary between T
IDL
and T
met
+T
IDL
.
In order to flatten the top surface of the IDL so that subsequent metal layers can be deposited using photolithography equipment with a typical depth of focus, prior art processes then planarize the top surface of the IDL. For example, chemical mechanical polishing (CMP) techniques are commonly used to planarize the surface of an IDL.
Conventional processes often require a relatively thick IDL to guarantee an uninterrupted IDL film over the metal pattern after planarization is completed. For example, a typical IDL could have a thickness of about 12,000 angstroms when initially deposited. A planarization process would then be performed, which could remove about 7000 angstroms or more, resulting in an IDL with T
IDL
equal to about 5000 angstroms above the metal on average.
The conventional planarization process described above requires a relatively thick IDL layer to guarantee an uninterrupted IDL film over a metal pattern for electrical isolation. The process of depositing thick IDL layers is time consuming, and affects manufacturing yields. In addition, the planarization process itself is complicated and time consuming. The more IDL that must be removed during the planarization procedure, the longer it takes to process each wafer, resulting in lower manufacturing yields and higher costs. Accordingly, the prior art IDL planarization processes are expensive and are not as efficient as desired. In addition, the more IDL that is removed, the less consistent the thickness across the production line. This inconsistency reduces product quality as well as requiring other processing steps to cover the wider range of incoming oxide thickness (i.e., via etches, subsequent metal fills).
One might consider reducing the amount of IDL that is removed through planarization so that T
IDL
is greater over the metal features. However, when vias are formed through the IDL to interconnect with the metal features, these vias would have higher aspect ratios (i.e., the ratio of the vias height to its width) than if the IDL overlying the metal features were thinner. Via openings with high aspect ratios are more difficult to fill with conductive material, and thus are more likely to be defectively manufactured or prone to failure.
One method for improving on the IDL planarization process is disclosed by Wemer Juengling in U.S. Pat. No. 5,981,384, issued Nov. 9, 1999. The method involves modifying the design of a metal layer's features to standardize the linear and diagonal spacing between nearest parallel and diagonal metal features. The design modifications yield a metal layer in which large open spaces are eliminated, and a relatively small, limited range of spaces, S
met
, between nearest parallel metal features is achieved. The thickness of the IDL layer, T
IDL
, is optimally chosen so that the trench between parallel metal features will be substantially filled with IDL material when it is deposited, thus eliminating the need for a subsequent planarization procedure. Essentially, using the method described by Juengling, the top surface of the IDL can be “self-planarized,” meaning that the top surface is substantially flatter when IDL is deposited, even without a separate planarization step.
FIG. 2
illustrates a side, cross-sectional view of the metal line layout of
FIG. 1
with enhanced metal features so as to standardize the spacing between the metal lines. As seen in
FIG. 2
, a substrate
206
has IDL
204
deposited over metal lines
202
. Each metal line
202
changed width as compared to
FIG. 1
, by including additional features
210
. These additional features
210
increase the resultant width of a metal line so that a standardized distance, S
met
220
, between nearest parallel metal lines and features is achieved. In addition, electrically isolated dummy features
222
are included where large areas of spacing existed on substrate
206
, within which there were no metal lines
202
. By standardizing the range of spaces S
met
220
, IDL
204
can be self-planarized at an altitude
224
of T
met
+T
IDL
, and only very narrow, “fused” trenches
230
remain. As long as T
IDL
is sufficiently great, these fused trenches
230
are insignificantly deep, eliminating other deeper trenches, and absent other deeper trenches
130
,
132
or depressed areas
134
(FIG.
1
). A subsequent planarization procedure is not necessary to achieve an acceptably planar surface of IDL
204
, but a slight IDL buff can be used to achieve an even more flat surface. Such a buff can improve the smoothness of subsequent metal depositions, and result in lower resistance metal lines.
FIG. 3
illustrates a top-down view of a metal line layer of an IC having standardized spacing between nearest parallel and diagonal metal features in accordance with the Juengling method. Metal lines
302
exist on a substrate within an area bounded by a guard ring
304
. Additional metal line features
310
have been added to existing metal lines
302
in order to standardize the spacing between nearest parallel and diagonal metal features. In addition, electrically isolated dummy features
322
have been added within the open space in which there are no metal lines.
Juengling states that the standard distance, S
met
320
, between nearest parallel metal features must be ≦2*T
IDL
. The reason for this is that most of the space between parallel metal features will be substantially filled with IDL material if S
met
is less than 2*T
IDL
, assuming perfect step coverage. Accordingly, even without a separate planarization process, only fused trenches (e.g., trench
230
,
FIG. 2
) should exist on the top surface of the IDL between the parallel metal features. The optimum space, S
met
, gets reduced for less than perfect step coverage IDL depositions. In addition, it is desirable to keep T
IDL
as low as possible so that vias that are subsequently formed through the IDL will not have an unreliably high aspect ratio.
Limitations of the Juen
Micro)n Technology, Inc.
Nelms David
Schwegman Lundberg Woessner & Kluth P.A.
Tran Mai-Huong
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