Integrated circuit with memory-less page table

Details Integrated circuit with memory-less page table Integrated circuit with memory-less page table

2005-06-24

2010-02-02

Chace, Christian P (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S203000, C710S026000, C710S074000

Reexamination Certificate

active

07657725

ABSTRACT:
A system is disclosed that comprises a processor, a memoryless first level page table addressable by the processor, and a second level page table stored in a memory coupled to the processor. The second level page table is addressable by at least one entry of the first level page table.

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patent: 1 528 474 (2005-05-01), None
Harrod, P. L., et al. “Boundary Scan Design for a Memory Controller,” IEE Colloquium on Application and Development of the Boundary-Scan Standard, Dec. 1990, pp. 3/1-3/2.

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