Integrated circuit with layout matched high speed lines

Details Integrated circuit with layout matched high speed lines Integrated circuit with layout matched high speed lines

2006-04-11

2006-04-11

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C326S041000, C326S047000, C326S101000, C326S102000, C326S044000, C326S044000, C326S044000

Reexamination Certificate

active

07028282

ABSTRACT:
A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without increasing the line-to-line capacitance. The capacitances, resistances, and RC time constants can be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform propagation delay.

REFERENCES:
patent: 4831497 (1989-05-01), Webster
patent: 5663908 (1997-09-01), Roohparvar
patent: 5761130 (1998-06-01), Roohparvar
patent: 5761131 (1998-06-01), Roohparvar
patent: 5774401 (1998-06-01), Roohparvar
patent: 5936877 (1999-08-01), Morgan
patent: 5995402 (1999-11-01), Morgan
patent: 6144575 (2000-11-01), Morgan
patent: 6205058 (2001-03-01), Roohparvar
patent: 6301141 (2001-10-01), Morgan
patent: 6301142 (2001-10-01), Morgan
patent: 6314012 (2001-11-01), Morgan
patent: 6320779 (2001-11-01), Morgan
patent: 6327167 (2001-12-01), Morgan
patent: 6526553 (2003-02-01), Andreev et al.
patent: 6564362 (2003-05-01), Osaki et al.
patent: 6588005 (2003-07-01), Kobayashi et al.

Affiliated with

Also associated with

Rating

Integrated circuit with layout matched high speed lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit with layout matched high speed lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit with layout matched high speed lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3612357