Integrated circuit with layered superlattice material and method

Details Integrated circuit with layered superlattice material and method Integrated circuit with layered superlattice material and method

1993-05-21

1995-11-21

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437190, H01L 21465

Patent

active

054686849

ABSTRACT:
A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layered superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.

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Mihara, Takashi, et al. "Feasibility for Memory Devices and Electrical Characterization of Newly Developed Fatigue Free Capacitors", 4th Annual Int'l Symposium on Integrated Ferroelectronics, 1992.

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