Integrated circuit with improved tub tie

Details Integrated circuit with improved tub tie Integrated circuit with improved tub tie

1989-07-03

1990-02-27

James, Andrew J.

357 86, 357 42, 357 231, H01L 2348

Patent

active

049050737

ABSTRACT:
When making CMOS logic circuits, for example an inverter, it is frequently necessary to connect the sources of the p and n channel transistors to their respective tubs (n and p, respectively). The prior art required either a large contact window covering both source and tub regions, or else two standard size contact windows. The present technique forms the tub tie connection by the use of the same silicide layer that is formed on the source/drain regions, which typically also forms a gate silicide in the self-aligned silicide (i.e., "salicide") process. A conventional window may then be used to connect the silicide tub tie (and hence the source/tub regions) to a power supply conductor. A space saving is obtained, and increased freedom for placing the power supply contact window is obtained.

REFERENCES:
patent: 4435896 (1984-03-01), Parillo et al.
patent: 4510670 (1985-04-01), Schwabe et al.
patent: 4621276 (1986-11-01), Malhi
patent: 4647956 (1987-03-01), Shrivastava et al.
patent: 4683488 (1987-07-01), Lee et al.
Semiconductor International, "Silicide Technology Spotlight", by Pieter Burggraff, May 1985.
"Titanium Disilicide Self-Aligned Source/Drain+Gate Technology" 1982 IEEE, IEDM 82, pp. 714-717, C. K. Lau, Y. C. See, D. B. Scott, J. M. Bridges, S. M. Perna and R. D. Davies VLSI Laboratory/Semiconductor Group CMOS division, Texas Inst.
"Titanium Nitride Local Interconnect Technology for VLSI", IEEE 1987, vol. ED-34, No. 3, Mar. 1987, pp. 682-687, Thomas E. Tang, Che-Chia Wei, Roger A. Haken, Thomas C. Holloway, Larry R. Hite, and Terence G. W. Blake.

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