Integrated circuit with improved static noise margin

Details Integrated circuit with improved static noise margin Integrated circuit with improved static noise margin

2008-02-06

2009-12-22

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Noise suppression

C365S154000

Reexamination Certificate

active

07636268

ABSTRACT:
A static random access memory (“SRAM”) has a plurality of SRAM cells connected to a word line. A static noise margin (“SNM”) detector controls a pull-down transistor that selectively couples the word line to a ground path. The SNM detector is configured to produce a first output signal in response to a SNM event that couples the word line to the ground path, and otherwise produces a second output signal that de-couples the word line from the ground path.

REFERENCES:
patent: 7099182 (2006-08-01), Ohtake et al.
patent: 2007/0030741 (2007-02-01), Nii et al.
patent: 2008/0043561 (2008-02-01), Wang et al.
Ohbayashi et al., “A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits,” IEEE Journal of Solid-State Circuits, Apr. 2007, pp. 820-829, vol. 42, No. 4.

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