Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-15
2001-04-17
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S360000, C257S531000
Reexamination Certificate
active
06218706
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to integrated circuits and more particularly to circuitry for protecting integrated circuit devices from overvoltages produced by electrostatic discharge (“ESD”) events applied to the inputs of the device.
Integrated circuit (“IC”) technology has advanced from generation to generation with ever decreasing circuit element dimensions and ever increasing circuit densities in the thumb-nail size semiconductor chips in which such circuits are fabricated. The thickness of insulation layers, such as gate oxide layers, has undergone a commensurate size reduction, with state-of-the-art process technologies using gate oxides under 100 Å in thickness. The dielectric breakdown of such ultrathin oxide insulating layers has made these recent generation devices more sensitive to overvoltages, requiring more sophisticated overvoltage protection schemes.
A common source of overvoltages to which IC devices are exposed is ESD, which can occur merely from human contact. Such ESD events can destroy an IC device by shorting through one or more of the thin oxide insulating layers in the device. Such ESD events can produce voltage spikes in the kilovolt range. According to standard industry practice, IC devices are expected to survive an ESD event of 2 kV without damage.
A complicating factor in designing overvoltage protection circuitry is that normal system voltages, which can be communicated as inputs to the IC device, are often higher than the voltage supply levels specified for normal operation of the IC device. For example, the most recent generations of IC devices, which are made using complementary metal-oxide-semiconductor (CMOS) technology, are designed to operate using a 3.3 volt supply, whereas IC devices of earlier generations were designed to operate using a 5.0 volt supply. Many existing systems are designed around the 5.0 volt standard, such that new pieces of electronic equipment using the latest IC devices that operate on a 3.3 volt supply must be adapted to receive 5.0 volt signals. This complicates the design of ESD protection circuitry since such circuitry for devices operating with 5.0 volt supplies was designed on the assumption that any input signal in excess of 5.0 volts would be an anomaly and indicative of the onset of an overvoltage event. However, for devices operating with 3.3 volt supplies and intended to tolerate 5.0 volt input signals, such input signals could be misinterpreted as possible ESD events thus triggering overvoltage protection circuitry unless such circuitry has been redesigned to accommodate normal input signals at levels of about 1.7 volts higher than the supply voltage. As of yet, no comprehensive solution to this problem has been found.
Thus, it would be desirable to provide a more effective solution to the problem experienced by 3.3 volt IC devices receiving 5.0 volt input signals. It would be desirable to provide overvoltage protection circuitry that protects the IC device from ESD events as well as making 3.3 volt IC devices compatible with 5.0 volt systems. In order to fully appreciate the improvement in the overvoltage protection circuitry of the present invention hereinafter described, the following description of the relevant prior art is provided with reference to
FIGS. 1-4
.
Referring to
FIG. 1
, a portion of an overvoltage protection circuit used in a prior art integrated circuit device is illustrated and designated generally by reference numeral
10
. The overvoltage protection circuit
10
is connected between a high voltage power bus or rail
12
and a low voltage power bus or rail
14
. The high voltage rail
12
is connected to a bonding pad (not shown) that receives from an external source a high voltage supply, conventionally designated V
DD
. The low voltage rail
14
is connected to a bonding pad (not shown) that receives from the external source a low voltage supply or ground, conventionally designated V
SS
.
The integrated circuit device of which the overvoltage circuit
10
is a part includes a plurality of input bonding pads P, only two of which are shown for ease of illustration. Each such input bonding pad P is connected between diodes D
1
and D
2
as shown, D
1
connecting the bonding pad to the low voltage rail
14
and D
2
connecting the bonding pad to the high voltage rail
12
. An overvoltage appearing on an input bonding pad P can be either a positive or negative voltage. The diodes D
1
and D
2
provide one form of overvoltage protection for the IC drive, diodes D
2
turning on to couple the input bonding pads to the V
DD
rail
12
when the overvoltage is positive and diodes D
1
turning on to couple the input bonding pads to the V
SS
rail
14
when the overvoltage is negative. In practice, each diode D
1
and diode D
2
are actually sets of relatively large diodes (e.g., four per set connected in parallel), providing low impedance ESD conduction paths from the input bonding pads P to the V
DD
and V
SS
rails.
The signal on each input bonding pad P is communicated to a corresponding receiver circuit
16
(labeled “Re”) through a node
18
disposed between the input bonding pad P and the anode of the corresponding diode D
2
as shown. An ESD clamp
20
corresponding to each input bonding pad P is connected between the node
18
and the low voltage rail
14
. Along with output circuits (not shown) the receiver circuits
16
comprise the sensitive input/output circuitry of the device that requires protection from overvoltages coming from external sources.
The ESD clamp
20
used to clamp each input bonding pad P is normally nonconductive but is triggered to become conductive in response to an ESD event appearing on the input bonding pads. Short duration voltage transients of several thousand volts can arise from human or machine handling of the IC device prior to installation in its end-use equipment. High voltage transients can arise from other sources after the IC device is installed in its end-use equipment. When an input bonding pad P experiences an ESD event, its ESD clamp
20
is triggered and quickly becomes conductive to limit the voltage differential seen by circuit elements of the IC device to a relatively low level that does not damage sensitive structures of the device. This ESD protection scheme requires an ESD clamp
20
for each input bonding pad P, and therefore requires a commitment of considerable chip space to implement.
One implementation of a suitable ESD clamp known in the art is shown in FIG.
2
. The ESD clamp
20
of
FIG. 2
has an N-channel MOS transistor T
C
connected between node
18
and the V
SS
rail
14
. A circuit for triggering transistor T
C
includes a Zener diode Z, resistors R
1
and R
2
and a diode D connected in series between node
18
and the V
SS
rail
14
. A node
22
is connected between resistors R
1
and R
2
to the gate of transistor T
C
. The Zener diode Z has its cathode connected to node
18
and its anode connected to resistor R
1
. Diode D has its anode connected to resistor R
2
and its cathode connected to the V
SS
rail
14
. Transistor T
C
has a parasitic bipolar mode of operation designated by transistor Q
C
shown in dashed outline. Transistor T
C
is made very wide with a short channel length so that it is capable of efficiently shunting the relatively high currents characteristic of an ESD event.
The values of elements Z, R
1
, R
2
and D are chosen so that the gate of transistor T
C
will see a voltage of about 3 volts when an ESD event occurs and the voltage on node
18
rises above a trigger voltage of about 7.0 to 7.5 volts. Once transistor T
C
is turned on by such an ESD event, bipolar conduction through transistor Q
C
will occur and will continue until the voltage on node
18
falls below the trigger voltage level. A more complete explanation of the operation of this particular ESD clamp
20
is provided in U.S. patent application entitled “Overvoltage Protection Device for MOS Integrated Circuits,” Ser. No. 08/712,058, filed Sep. 10, 1996.
Another ESD clamp or shunt int
Imbruglia Antonio
Waggoner Charles D.
Zambrano Raffaele
Galanthay Theodore E.
Jorgenson Lisa K.
Loke Steven
STMicroelectronics Inc.
Thoma Peter J.
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