Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-06-26
2004-05-11
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S066000, C711S171000
Reexamination Certificate
active
06735661
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the structure and design of integrated circuits (ICs), in particular to the embedding or integration of a non-volatile, flash memory into an IC. This embedding or integration of non-volatile memory with a microprocessor is often desired or even required for ICs to be used in mobile phones, personal digital assistants, in GPS applications for automobile or other navigation purposes.
BACKGROUND OF THE INVENTION
Embedding a flash memory into a chip leads to certain problems that have to be solved before such embedding exhibits the expected advantages. One of the issues is that, by “nature”, the access times of usual flash memories differ significantly from the access times of the other components on the IC.
Thus, the present invention intends to provide a solution to the specific problematic aspect that the absolute speed of flash memory is quite low compared to many components on a given IC, in particular compared to any read-only-memory (ROM) or today's fast microprocessors and/or their buses.
A flash or other non-volatile memory embedded into an IC is, for example, shown in the published PCT applications WO 0025208 by Feldman et al. and WO 0025250 by Ozcelik et al. Neither of these two patent publications addresses, however, the above-identified issue, namely the differing data path widths between flash memory and processor(s) on the IC. U.S. Pat. No. 5,493,534 by Mok gets a little closer by showing a electronically programmable and erasable program memory for a microcontroller embedded on a chip which is isolated, so-to-speak, from the processor bus by buffers. But again, Mok does not give a clear and convincing solution to the problem of the differing data widths of the bus and the flash memory.
To really exploit the potential of a flash memory integrated with one or more microprocessors, the flash memory's overall access time must keep pace with the microprocessors' clocking rates to achieve the expected performance. Since, as mentioned above, flash memories usually have relatively long access times, problems are unavoidable when operating an associated microprocessor at a higher clocking rate than the flash memory access time.
SUMMARY OF THE INVENTION
Here, the present invention provides a solution. It describes a way for improving the function of embedded flash memory in a processor environment on an IC, with the emphasis on maximizing performance, by proposing a number of inventive measures which serve to increase the overall speed of such ICs.
In brief, the present invention solves the above-identified issues by one or both of two measures:
1. One measure is to increase the embedded flash memory's data word width to compensate for its access time performance.
2. The other measure is to provide a data cache, in particular by using intermediate data storage registers as single or multiple line data caches.
There are other additions and variations envisageable from the following description of an embodiment which describes an IC with a flash memory, a dedicated flash bus, and a number of flash memory supporting blocks, in particular the connections or bridges to the processor (or even multiprocessor) environment. These bridges will be called “flash bridges” in the following.
The first above-mentioned measure is to increase the data word width of the embedded flash memory to a multiple of the width of processor bus. A flash bridge connecting the flash memory with the processor bus then accesses the flash memory by swapping a whole block of processor data words into an intermediate storage register at one time. The processor can now fetch a word at a time from the intermediate storage register without the flash memory being accessed on every processor fetch cycle. Of course, multiple intermediate storage registers may be used.
The second above-mentioned measure is to provide an address tag register which allows using the intermediate data storage registers as a cache with one or more lines. Recently used accesses may now directly be supplied by the intermediate storage registers, avoiding flash memory accesses even if the microprocessor accesses are not strictly sequential. Only if the required address is not in the cache, the flash memory must be accessed and the intermediate storage registers will be updated. This caching concept is used as “secondary cache” only for the flash memory and differs insofar from common caches, i.e. the flash bridge mentioned above is used as a secondary cache for buffer accesses to the flash memory only. So-called secondary caches are placed in series with a primary cache which is directly connected to the processor. Their principle is well known in the art and need not be described further.
In the following, an example for an implementation of the present invention will be shown. Three figures illustrate this implementation on an IC with an embedded flash memory.
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Gappisch Steffen
Gelke Hans-Joachim
Koch Stefan
Koninklijke Philips Electronics , N.V.
Myers Paul R.
Ure Michael J.
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