Integrated circuit with ESD protection circuit

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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C361S091100, C361S111000

Reexamination Certificate

active

07463466

ABSTRACT:
An integrated circuit (IC) having an electrostatic discharge (ESD) protection circuit therein is provided. The IC comprises a plurality of bonding pads, a plurality of ESD units, a first ESD bus and a second ESD bus. The first ESD bus has no direct connection with any power pad of the IC. Each ESD unit comprises a first diode, a second diode and an ESD clamping device. Due to the one-to-one correspondent of each bonding pad with an ESD unit, the present invention ensures ESD continuity through a continuous charge dissipation path no matter what kind of pin-to-pin ESD test the IC is undergoing or how many power sources the IC has. In addition, a bonding pad over active circuitry (BOAC) structure can also be deployed in the present invention to provide a better ESD protection for the whole IC chip.

REFERENCES:
patent: 5652689 (1997-07-01), Yuan
patent: 5654862 (1997-08-01), Worley et al.
patent: 5963409 (1999-10-01), Chang
patent: 6072219 (2000-06-01), Ker et al.
patent: 6144542 (2000-11-01), Ker et al.
patent: 6157065 (2000-12-01), Huang et al.
patent: 6465768 (2002-10-01), Ker et al.
patent: 6603177 (2003-08-01), Tang et al.
patent: 6646840 (2003-11-01), Sugerman et al.
patent: 6867461 (2005-03-01), Ker et al.
patent: 2005/0286186 (2005-12-01), Chang
Article titled“Substrate-Triggered ESD Protection Circuit Without Extra Process Modification”, jointly authored by Ker et al., IEEE Journal of Solid-State Circuits, vol. 38, No. 2. Feb. 2003, pp. 295-302.
Article titled “A Fail-Safe ESD Protection Circuit with 23D IF Linear Capacitance for High-Speed/High-Precision 0.18 μm CMOS I/O Application” jointly authored by Lin et al., IEDM Journal, vol. 13, No. 6, 2002 pp. 349-352.
Article titled “Substrate Pump NMOS for ESD Protection Applications” jointly authored by Duvvury et al., EOS/ESD Symposium, vol. 1A, No. 2.1-2.11, pp. 00.7-00.17.

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