Integrated circuit with EPROM cells

Details Integrated circuit with EPROM cells Integrated circuit with EPROM cells

1994-12-15

1997-03-11

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257378, 257550, H01L 2706, H01L 27115

Patent

active

056104219

ABSTRACT:
An integrated circuit structure is disclosed wherein an EPROM cell has an active area formed by the same operations as are carried out to form a P region intended to contain an N-channel MOS transistor, source and drain regions formed by the same operations as are carried out to form the source and drain regions of said transistor, a control electrode consisting of an N+ region formed by the same operations as are carried out to form deep regions intended to contact buried N+ regions, and a floating gate electrode consisting of a layer of conductive material formed by the same operations as are carried out to form the gate electrodes of the MOS transistors in the integrated circuit.
The EPROM cell can, therefore, be formed in a mixed integrated circuit with no need for purposely added processing steps.

REFERENCES:
patent: 4586238 (1986-05-01), Yatsuda et al.
patent: 5264716 (1993-11-01), Kenney
patent: 5378909 (1995-01-01), Chang et al.
patent: 5432740 (1995-07-01), D'Arrigo et al.
Ohzone et al., "An 8K .times. 8 Bit Static MOS RAM Fabricated by n-MOS
-Well CMOS Technology," IEEE Journal of Solid-State Circuits, SC-15(5):pp. 854-861, Oct. 1980.

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