Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2004-07-21
2008-03-18
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S052000, C710S056000
Reexamination Certificate
active
07346726
ABSTRACT:
An integrated circuit comprising a plurality of modules (M1to M5, CPU) for processing applications, a global memory (GM), which can be shared by said plurality of modules (M1to M5, CPU), an interconnect means (IM) for interconnecting said modules (M1to M5, CPU) and said global memory (GM) based on a plurality of communication services (C1, C2) is provided. Said integrated circuit further comprises at least one communication managing unit (CMU) for managing the communication between said plurality of modules (M1to M5), wherein said communication managing unit (CMU) receives a request for a communication between at least two of said modules (M1to M5, CPU) and dynamically selects one of said plurality of communication services (C1, C2) as basis for the requested communication between said modules (MI to M5, CPU).
REFERENCES:
patent: 5734843 (1998-03-01), Gephardt et al.
patent: 5935232 (1999-08-01), Lambrecht et al.
patent: 2006/0095920 (2006-05-01), Goossens
patent: 2006/0123154 (2006-06-01), George
patent: 2006/0274786 (2006-12-01), Malalur et al.
Burchard Artur Tadeusz
Harmsze Françoise Jeannette
Kenter Harm Jan Hiltjo Nanno
Auve Glenn A.
NXP B.V.
Zawilski Peter
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