Integrated circuit with differing gate oxide thickness

Details Integrated circuit with differing gate oxide thickness Integrated circuit with differing gate oxide thickness

1998-12-08

2003-12-09

Wiczewski, Mary (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S374000, C257S390000, C257S391000, C257S607000, C438S981000, C438S275000, C438S276000, C438S217000

Reexamination Certificate

active

06661061

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of semiconductor processing and more particularly to an MOS integrated circuit in which select transistors are fabricated with a thinner gate oxide than the remaining transistors.
2. Description of the Relevant Art
Very large scale integrated (VLSI) metal-oxide-semiconductor (“MOS”) circuits include a large number of interconnected transistors formed in a silicon substrate. Typically, the gate electrode of the MOS transistor functions as the transistor's input. The transistor is typically activated or turned on by driving the gate voltage (V
G
) to a threshold value, the threshold voltage (V
T
). The drain current (I
D
) of an MOS transistor typically serves as the transistor's output. Because the gate electrode of each transistor has a small but finite capacitance associated with it, the gate electrode cannot instantaneously achieve a desired change in voltage. Instead, a finite amount of time is required to charge the small gate capacitor to the appropriate voltage level. The amount of time required for a gate electrode to achieve a threshold level can be reduced by decreasing the capacitance of the gate electrode or increasing the drain current of transistors from preceding stages. Generally, for small values of drain voltage, V
D
, (i.e., V
D
<V
G
−V
T
) the drain current I
D
of an MOS transistor increases linearly with the drain voltage (assuming V
G
≧V
T
). As V
D
is increased beyond this linear region, however, I
D
levels off and becomes independent, to a first order approximation, of V
D
. This value of I
D
is commonly referred to as the saturated drain current, I
Dsat
. In other words, I
Dsat
is the maximum drain current produced by an MOS transistor operating under normal biasing (i.e., V
D
≡V
CC
, |V
G
|≧|V
T
|, and V
SS
=0 V) for a given gate voltage. I
Dsat
is, therefore, a direct measure of the potential speed of an MOS circuit. Increasing I
Dsat
increases the integrated circuit's performance by enabling each transistor to drive subsequent stages of transistors to their threshold voltage in less time.
In the linear region, I
D
=k (V
G
−V
DS
/2) V
DS
, where k=&mgr;C
OX
W/L. Inspection of this equation reveals that I
D
can be increased by increasing the oxide capacitance C
OX
. In addition to increasing k, a larger oxide capacitance reduces the threshold voltages V
T
for the general case in which the total charge Q
TOT
trapped within the oxide and trapped at the oxide-silicon interface is relatively small. The capacitance, C
OX
, of an MOS transistor is closely approximated by a parallel plate capacitor such that C
ox
≡A∈/t
OX
where A is the area of the gate structure, ∈ is the permitivity of the dielectric, and t
OX
is the oxide thickness. Because it is undesirable to increase the area of the gate and difficult to alter the dielectric, increasing the capacitance C
OX
must be accomplished by decreasing the oxide thickness t
OX
.
In many complementary metal oxides semiconductor (CMOS) processes, the gate structures for the transistors are formed from heavily doped polysilicon. To achieve a degree of symmetry between the p-channel and n-channel transistors, it is not uncommon to dope the gate structures of the n-channel devices with an n-type impurity such as arsenic or phosphorous while doping the gate structures of the p-channel devices with a p-type impurity such as boron. The doping of the p-channel polysilicon gate with boron can become problematic for thin gate oxide structures due to the relatively rapid rate at which boron diffuses through silicon dioxide.
In very thin oxide structures, (i.e., t
OX
≦3 nm), boron ions from the heavily doped p+ polysilicon can diffuse through the oxide into the silicon bulk, thereby shifting the threshold voltage V
T
of the p-channel devices. This limitation on the thickness of the p-channel oxide has typically limited the oxide thickness of the n-channel devices as well because it is highly desirable from a manufacturing perspective to grow the capacitor or gate oxide nonselectively, (i.e., grow the gate across the entire wafer rather than in selected or masked regions of the wafer). The nonselective oxide growth tends to result in oxide thicknesses that are uniform across the entire wafer. Furthermore, conventional processing considerations teach away from multiple gate oxide thicknesses within a technology because of the nonsymetry that would result from the use of such multiple thickness oxide technologies.
The desire to maintain symmetry has undesirably limited the potential performance of the n-channel devices in certain CMOS processes by restricting the minimum thickness of the gate oxide. More generally, symmetry considerations have prohibited designs in which selected critical transistors could be designated as high performance, thin oxide transistors. It would, therefore, be desirable to achieve a semiconductor manufacturing process in which selected transistors incorporate a gate oxide having a first thickness while the remaining transistors have a second gate oxide thickness without unduly complicating the process flow.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by a manufacturing process capable of producing at least two different oxide thicknesses. Nitrogen is incorporated into selected areas of the silicon prior to the formation of the gate oxide. A subsequent gate oxide cycle results in a first oxide thickness over the nitrogen regions of the silicon and a second gate oxide thickness over the remaining regions of the silicon. The first oxide thickness will tend to be less than the second oxide thickness due to the tendency of the nitrogen to retard the silicon oxidation rate. In this manner, multiple gate oxide thicknesses can be achieved without unduly complicating the manufacturing process.
Broadly speaking, the present invention contemplates a semiconductor process. A semiconductive substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon. Preferably, the step of introducing the nitrogen species impurity distribution into the semiconductor substrate is accomplished by thermally oxidizing the first substrate region in a nitrogen bearing ambient. In a presently preferred embodiment, the nitrogen bearing ambient includes N
2
O, NH
3
, O
2
and HCl in an approximate ratio of 60:30:7:3. In alternative embodiments the nitrogen bearing ambient includes NO, O
2
and HCl in an approximate ratio of 90:7:3 or N
2
O, O
2
and HCl in an approximate ratio of 90:7:3. The introduction of the nitrogen species impurity into first substrate region
102
may alternatively be accomplished with rapid thermal anneal processing.
In one embodiment, an initial oxide layer is formed on an upper surface of the semiconductor substrate prior to thermally oxidizing the first substrate region. The formation of the initial oxide layer, in one embodiment, is followed by forming a silicon nitride layer on the initial oxide layer and removing portions of the silicon nitride layer over the first region of the semiconductor substrate. In alternative embodiments, the initial oxide layer can comprise a thermal oxide or an oxide deposited in a CVD reactor.
The present invention further con

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