Integrated circuit with control circuit for performing...

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C365S233100

Reexamination Certificate

active

07872931

ABSTRACT:
An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for the retention test.

REFERENCES:
patent: 6366514 (2002-04-01), Chien
patent: 6496947 (2002-12-01), Schwarz
patent: 7123542 (2006-10-01), Fekih-Romdhane et al.
patent: 7164613 (2007-01-01), Fekih-Romdhane et al.
patent: 7362633 (2008-04-01), Fekih-Romdhane
patent: 2005/0248755 (2005-11-01), Chou et al.
patent: 2006/0198207 (2006-09-01), Ishikawa
patent: 2006/0294443 (2006-12-01), Fekih-Romdhane
patent: 2007/0226553 (2007-09-01), Fekih-Romdhane et al.
patent: 2007/0234162 (2007-10-01), Barth
patent: 2008/0159031 (2008-07-01), Fekih-Romdhane

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