Integrated circuit with built-in processor and internal bus...

Details Integrated circuit with built-in processor and internal bus... Integrated circuit with built-in processor and internal bus...

2000-02-09

2004-05-18

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C712S032000

Reexamination Certificate

active

06738853

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an integrated circuit with built-in processor having a processor, an internal bus connected with the processor and an external output terminal for accessing an external memory, and relates to an internal bus observing method in the integrated circuit with built-in processor. More specifically, this invention relates to an integrated circuit with built-in processor and an internal bus observing method in the integrated circuit with built-in processor which outputs a signal of the internal bus to outside at the time of debug to observe the internal bus.
BACKGROUND OF THE INVENTION
In an integrated circuit with built-in processor, in order to verify functions and analyze an operation of the processor, it is important to observe the internal bus from outside at the time of debugging. There is an LSI with built-in CPU which is capable of observing the internal bus from the outside as the conventional integrated circuit with built-in processor.
FIG. 8
is a block diagram showing a schematic configuration of an LSI with built-in CPU.
A conventional LSI with built-in CPU
51
is basically constituted so as to include a CPU core (processor)
52
for executing a process according to programs stored in an external memory
64
, an SRAM
53
, a DRAM
54
, a DMAC (direct memory access controller)
55
for controlling direct memory access, a user logic
56
designed by a user, a peripheral I/O
57
for executing input/output for a peripheral device, a CSC (chip select controller)
58
for accessing the external memory
64
, an internal CPU bus (internal bus)
59
for connecting these sections so that communication among the sections is possible, an external memory access-use external pin (external output terminal)
67
for accessing the external memory (an external memory)
64
, an external memory access bus
60
for connecting the CSC
58
with the external memory
64
via the external memory access-use external pin
67
so that communication therebetween is possible, a chip select signal-use signal line
62
for a chip select signal outputted from the CSC
58
to the external memory
64
, a test pin
66
for setting a function of the LSI with built-in CPU
51
to a mode for observing the internal CPU bus
59
, a bus selector
61
for selecting signals of the internal CPU bus
59
or signals of the user logic
56
according to the setting of the test pin
66
so as to output the selected signals, and a logic analyzer (digital waveform observing unit)
65
for observing the signals of the internal CPU bus
59
outputted from the bus selector
61
.
There will be described below the operation of this conventional LSI with built-in CPU
51
. When the internal CPU bus
59
is to be observed, the LSI with built-in CPU
51
is first set to a mode for observing the internal CPU bus
59
by the test pin
66
. As a result, the bus selector
61
selects the signals of the internal CPU bus
59
. The signals of the internal CPU bus
59
are outputted from a user logic-use external pin and are observed by the logic analyzer
65
. In this case, since the user logic-use external pin is used for observing the internal CPU bus
59
, the function of the user logic
56
is limited.
Here, the signals of the internal CPU bus
59
may be outputted from another external pin such as a peripheral I/O-use external pin and observed. Also in this case, since the peripheral I/O-use external pin is used for observing the internal CPU bus
59
, the function of the peripheral I/O
57
is limited. However, since the external memory access-use external pin
67
is required to be used for executing a program, the pin
67
is not used for observing the internal CPU bus
59
.
However, according to the above conventional art, since the functions of the user logic
56
and the peripheral I/O
57
are limited, the internal bus cannot be observed when all the operating functions are actually executed. Therefore, there is a disadvantage that the suitable functions cannot be verified and the operation of the processor cannot be analyzed. Moreover, when the number of external output terminals other than the external output terminal for accessing the external memory is small, a number of terminals to be used for observing the internal bus is limited. As a result, the signals of the internal bus cannot be observed all at once, which is troublesome, and the cost rises.
SUMMARY OF THE INVENTION
The present invention has been made with such points in view. It is an object of the present invention to provide an integrated circuit with built-in processor and an internal bus observing method which are capable of observing an internal bus when all operating functions are actually operated and capable of verifying the suitable functions and analyzing an operation of the processor.
According to one aspect of this invention, an output unit outputs the signals of the internal bus to the external output terminal for accessing the external memory when the external memory is not being accessed, namely, at timing of intervals between the operations for accessing the external memory. As a result, it is not necessary to use external output terminals other than the external output terminal for accessing the external memory such as external output terminals for a user logic and a peripheral I/O for observing the internal bus.
Further, a delay unit is provided which delays the signals of the internal bus, and the output unit outputs the signals of the internal bus delayed by the delay unit to the external output terminal. As a result, even in the case where a cycle of accessing the external memory and a cycle of the internal bus are delayed (conflict with each other), the signals of the internal bus are delayed so as to be capable of being outputted by delayed time.
Further, a notification unit is provided which outputs a notification signal dedicated for notifying as to whether or not the external memory is being accessed, and the output unit outputs the signals of the internal bus to the external output terminal based on the notification signal outputted from the notification unit. As a result, since notifying is made as to whether or not the external memory is accessed, it is not necessary to input a signal for controlling the external memory such as a chip select signal to the output unit.
According to another aspect of this invention, a output step is provided in which the signals of the internal bus are outputted to the external memory access-use external output terminal when the external memory is not being accessed, namely, at timing of an interval between the external memory access operations, and a observation step is provided for observing the signals of the internal bus, which were outputted to the external output terminal in the output step. As a result, it is not necessary to use external output terminals other than the external memory access-use external output terminal such as external output terminals for the user logic and peripheral I/O for observing the internal bus.
Further, a delaying step is provided in which the signals of the internal bus are delayed, and in the output step the signals of the internal bus delayed in the delay step are outputted to the external output terminal. As a result, even in the case where the cycle of accessing the external memory and the internal bus cycle are delayed (conflict with each other), the signals of the internal bus are delayed by delayed time so as to be capable of being outputted.
Further, a notification step is provided in which a notification signal dedicated for notifying as to whether or not the external memory is accessed is outputted, and in the output step the signals of the internal bus are outputted to the external output terminal based on the notification signal outputted in the notification step. As a result, it is not necessary to use a signal for controlling the external memory such as a chip select signal in order to notifying as to whether or not the external memory is being accessed.


REFERENCES:
patent: 4777355 (1988-10

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