Integrated circuit with bonding layer over active circuitry

Details Integrated circuit with bonding layer over active circuitry Integrated circuit with bonding layer over active circuitry

2002-07-10

2004-01-27

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

C438S613000

Reexamination Certificate

active

06683380

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits (IC's), and more particularly to IC's having a bonding surface that permits wire bonds or flip chip bumps to be fabricated on top of the IC's active circuitry rather than in the IC's periphery.
BACKGROUND OF THE INVENTION
Electronic devices made using semiconductor fabrication techniques (silicon integrated circuits), use bond pads for bonding electrical connecting wires or flip chip bumps to the device. Typically, the bond pads, as well as their buses, are placed in the periphery of the integrated circuit (IC), outside the area containing active components. This conventional structure for the bond pads adds to the required real estate of the IC, which reduces production efficiency and increases the size of each IC. It also adds resistance to the current path and limits the bond pitch.
FIG. 5
illustrates an integrated circuit chip
2
according to the prior art having bond pads located in its periphery. Integrated circuit chip
2
includes a scribe area
3
along the edge of IC chip
2
from which IC chip
2
is cut from a wafer to separate it from other IC chips on the wafer. A pad ring area
4
is located adjacent to scribe area
3
. Pad ring area
4
surrounds active circuit region
8
. The electrical circuits and components that provide functionality to IC chip
2
are located within active circuit region
8
. Bond pads
5
are formed in pad ring area
4
with wires
6
bonded to bond pads
5
by wire bonds
7
. As seen in
FIG. 5
, the location of bond pads
5
outside of the active circuit region
8
significantly increases the size of IC chip
2
.
SUMMARY OF THE INVENTION
One aspect of the invention is a method of fabricating a bonding surface on a wafer from which integrated circuits (IC's) will be made. The wafer has at least one metallization layer electrically coupled to active circuitry formed in a semiconductor layer. A protective coating is deposited over the metallization layer. Vias are etched or otherwise formed through the protective coating to the metallization layer. A seed metal layer is then deposited over the entire surface of the wafer. A plating pattern, such as a photoresist pattern, is defined over the seed metal layer, resulting in exposed portions of the seed metal layer (vias) where connections are to be made to the metallization layer. A series of plating layers are then formed, with the plating material filling the vias and forming a desired pattern on the surface of the wafer. Specifically, the plating layers comprise at least a support layer then a wire bonding/flip chip connection layer. At each via, the seed metal layer, the support layer, and the wire bonding/flip chip connection layer form a “connector stack” that electrically connects the plating layer to the metallization layer. Finally, the seed metal layer, where it has not been plated, is removed. The plating layer forms a bonding surface for wire bonding or flip chip bumps for purposes of external electrical connections to the IC.
An advantage of the invention is that it permits bond pads or flip chip bumps to be fabricated directly over the active circuitry of an IC, rather than next to the active circuitry in the IC's periphery. As a result, the area of the IC is reduced. Also, the ability to perform wire bonding directly over the active circuitry relaxes bond pitch constraints and reduces interconnect parasitic resistance.
The plated bonding surface permits either aluminum or gold, mixed aluminum and gold wire bonding or flip chip bonding. At the same time, the bonding surface protects the underlying active circuitry from damage during the bonding process.


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Harper, Electronic Packaging and Interconnection Handbook, 1991, McGraw-Hill, 6.71-73.*
U.S. 2002/0011674 A1 patent application Publication.
U.S. 2002/0000671 A1 patent application Publication.

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