Integrated circuit with bit lines positioned in different...

Details Integrated circuit with bit lines positioned in different... Integrated circuit with bit lines positioned in different...

2011-01-18

2011-01-18

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S150000, C365S185130, C365S205000

Reexamination Certificate

active

07872902

ABSTRACT:
An integrated circuit includes a memory cell array including a plurality of memory cells. A first plurality of bit lines is positioned in a first plane. The first plurality of bit lines is electrically coupled to a first set of the memory cells. A second plurality of bit lines is positioned in a second plane that is different than the first plane. The second plurality of bit lines is electrically coupled to a second set of the memory cells.

REFERENCES:
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patent: 5430678 (1995-07-01), Tomita et al.
patent: 6304479 (2001-10-01), Vollrath et al.
patent: 6400621 (2002-06-01), Hidaka et al.
patent: 6967370 (2005-11-01), Schroder et al.
patent: 7376026 (2008-05-01), Vollrath et al.
patent: 2007/0211509 (2007-09-01), Vollrath

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