Integrated circuit with bit error test capability

Details Integrated circuit with bit error test capability Integrated circuit with bit error test capability

2003-07-15

2009-11-17

Raymond, Edward (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

Reexamination Certificate

active

07620515

ABSTRACT:
An integrated circuit (10), preferably a field programmable gate array—FPGA or an application specific integrated circuit—ASIC—, comprises a level comparator (30) for comparing a level of a comparator input signal and correspondingly providing a comparator output signal (COS). A sampling unit (40) is coupled to the level comparator (30) for sampling (SAM) the comparator output signal (COS). A bit error test unit (60) receives the sampled comparator output signal (SAM) and determine therefrom an indication of a bit error in a sequence of the sampled comparator output signal (SAM).

REFERENCES:
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patent: 7069488 (2006-06-01), Moll et al.
patent: 7263151 (2007-08-01), Momtaz et al.
patent: 2003/0023912 (2003-01-01), Lesea
patent: 2003/0031282 (2003-02-01), Mc Cormak et al.
patent: WO 01/20452 (2001-03-01), None
patent: WO 01/73465 (2001-10-01), None
“SCAN921023 and SACN921224 20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1”.

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