Integrated circuit with a reduced pad bump area and the...

Details Integrated circuit with a reduced pad bump area and the... Integrated circuit with a reduced pad bump area and the...

2006-10-23

2009-06-02

Lee, Calvin (Department: 2892)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257S758000

Reexamination Certificate

active

07541274

ABSTRACT:
An integrated circuit with a reduced pad bump area and the manufacturing method thereof are disclosed. The integrated circuit includes a semiconductor substrate, an interconnection layer, a passivation layer, and at least a bump. The semiconductor substrate has a semiconductor device thereon. The interconnection layer is disposed on the semiconductor substrate and topped with a top metal layer which at least includes a bonding pad and a conductive line. The passivation layer is disposed on the interconnection layer and has at least an opening to expose the bonding pad. The bump is disposed on the passivation layer to connect the bonding pad through the opening and is extended to a coverage area not directly over the bonding pad.

REFERENCES:
patent: 6706584 (2004-03-01), List et al.
patent: 7462558 (2008-12-01), Lin et al.
patent: 2007/0007662 (2007-01-01), Shindo et al.

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