Integrated circuit with a recessed conductive layer

Details Integrated circuit with a recessed conductive layer Integrated circuit with a recessed conductive layer

2002-01-29

2003-11-25

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S206000, C438S245000, C438S386000, C438S391000, C257S301000, C257S302000, C257S328000

Reexamination Certificate

active

06653229

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for making integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits are made by forming on a substrate, such as a silicon wafer, layers of conductive material that are separated by layers of dielectric material. Trenches may be etched into the dielectric layers, e.g., when forming single or dual damascene interconnect structures, then filled with a conductive material to form conductive layers.
In the conventional process, generally, the surface of a conductive layer formed in a trench is substantially flush with the surface of the dielectric layer or layers that insulate the conductive layer. In some circumstances, such an attribute may be undesirable. Take, for example, an integrated circuit that includes a dielectric layer made from a low dielectric constant material. Such a dielectric layer may ensure that a conductive layer's RC related delays are reduced. Such a layer, however, may have poor mechanical integrity. To improve the mechanical strength of the overall dielectric layer, a second dielectric layer, having a higher dielectric constant and superior mechanical strength, may be formed on the layer with the low dielectric constant. Because that second layer has a relatively high dielectric constant, however, some of the RC delay reducing benefit, which the low dielectric constant material provides, will be lost when such a layer is used to form part of the overall dielectric layer.
There is thus a need for an improved method for making an integrated circuit in which the surface of a conductive layer formed in a trench is recessed from the surface of the dielectric layer or layers that insulate the conductive layer. There is also a need for such a method that produces an integrated circuit that has acceptable RC characteristics, while using mechanically strong dielectric layers to separate the conductive layers. This application describes such a method.
SUMMARY OF THE INVENTION
An improved method for making an integrated circuit is described. That method comprises forming a dielectric layer on a substrate, then etching a trench into that layer. After filling the trench with a conductive material, the conductive material is electropolished to form a recessed conductive layer within the dielectric layer. In a preferred embodiment, a dielectric layer having a relatively high dielectric constant is formed on top of a dielectric layer having a relatively low dielectric constant. A trench is etched through the upper layer and into the lower layer, then filled with a conductive material. That conductive material is then electropolished to form a recessed conductive layer that is separated from the dielectric layer that has a relatively high dielectric constant.


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Robert J. Contolini et al., “A Copper Via Plug Process by Electrochemical Planarizsation” 1993 VLSI Multilevel Interconnection Conference, Jun. 8-9, 1993, Santa Clara, Ca.

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