Integrated circuit wiring and fabricating method thereof

Details Integrated circuit wiring and fabricating method thereof Integrated circuit wiring and fabricating method thereof

2000-12-07

2001-11-20

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000, C438S597000, C438S649000, C438S655000, C438S682000

Reexamination Certificate

active

06319806

ABSTRACT:

This application claims the benefit of Korean Application No. 5760/2000, filed in Korea on Feb. 8, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit wiring and a fabricating method thereof and in particular, to an integrated circuit wiring capable of reducing contact resistance between lines constituting the integrated circuit and a fabricating method thereof.
2. Description of the Background Art
As the density of an integrated device increases, the size of elements constituting the integrated device is decreased more and more. Accordingly, the sectional area of a line such as a word line and a bit line, which constitute the integrated device, also decreases, and thus the resistance of the line is increased. To solve this problem, a method of forming wiring using polycide with a stack structure of silicon and silicide has been employed recently.
Wiring using a silicide as a polycide has an excellent characteristics compared to wiring formed of silicon or metal. Silicide material has lower resistivity than silicon and exibits strong oxidation-resistance. Even when exposed to an oxygen atmosphere, only silicide material sufaces oxidize.
FIGS. 1A through 1H
sequentially illustrate a conventional method of fabricating a word line and a bit line using polycide.
First, as shown in
FIG. 1A
, a gate oxide film
2
, a doped first silicon film
3
, a first silicide film
4
, a silicon oxide film
5
, and a first silicon nitride film
6
are sequentially deposited and stacked on the upper surface of a substantially single crystal semiconductor substrate
1
. The first silicon film
3
is formed of polysilicon or amorphous silicon, and the first silicide film
4
is mostly formed of tungsten silicide (WSi
x
). The silicon oxide film
5
is formed of SiO
2
, and the first silicon nitride film
6
is formed of Si
3
N
4
.
Next, as shown in
FIG. 1B
, a photoresist film (not shown) is applied on the upper surface of the first silicon nitride film
6
to thereafter form a first photoresist film pattern
7
by exposure and developing processes. Then, using the first photoresist film pattern
7
as a mask, a silicon nitride film
6
′ and a silicon oxide film pattern
5
′ are formed by sequentially patterning the first silicon nitride film
6
and the silicon oxide film
5
.
Next, as shown in
FIG. 1C
, the photoresist film
7
is removed. Then, using the silicon nitride film
6
′ and the silicon oxide film pattern
5
′ as a hard mask, a word line
20
formed of a first silicide film pattern
4
′ and a first silicon film pattern
3
′ is formed by sequentially patterning the first silicide film
4
and the first silicon film
3
.
In the process of forming the first silicide film pattern
4
′ and the first silicon film pattern
3
′, etchant gas concentrates on part ‘A’ of
FIG. 1C
resulting in overetching a portion of the gate oxide in part ‘A’, thus damaging the gate oxide. Since this damage to the gate oxide film results in undesirable device characteristics, reoxidation is performed in an oxygen atmosphere to repair damage to the gate oxide film.
Taking the case where first silicide film pattern
4
′ is formed of tungsten silicide (WSi
x
), for example, the grain size is about 300 Å at the initial stage of deposition. However, as crystallization of tungsten silicide proceeds after an annealing treatment, such as reoxidation or planation, grain size increases to about 700 Å~1200 Å. When silicon atoms are not properly provided in this process of crystallization, voids may occur between grains. (S. G. Telford et al., “Chemically Vapor Deposited Tungsten Silicide Films Using Dichlorosiane in a Single Wafer Reactor”, vol. 140, No. 12, 1993, pp. 3689~3701). When tungsten silicide is so crystallized, a path forms where atoms easily diffuse through voids and grain boundaries between grains. The crystallization thus described can occur not only to tungsten silicide, but also to other kinds of silicide.
In addition, silicon in first silicide film pattern
4
′ has a high degree of oxidation compared to silicon in first silicon film pattern
3
′ , resulting in oxidation of silicon located near surfaces of first silicide film pattern
4
′, thus forming an SiO
2
film on these surfaces. As the oxidation proceeds on the surfaces of first silicide film pattern
4
′, silicon located in first silicide film pattern
4
′ diffuses near surfaces of the film, resulting in silicon deficiency in first silicide film pattern
4
′. (Chue-sang Yoo et al., “Si/W Ratio Changes and Film Peeling During Polycide Annealing,” vol.
29
, No. 11, 1990. pp.2535~2540). In order to compensate this deficiency, silicon atoms diffuse from first silicon film pattern
3
′ near first silicide film pattern
4
′ into first silicide film pattern
4
′ through the grain boundaries and voids. However, dopant atoms from first silicon film pattern
3
′ also diffuse into first silicide film pattern
4
′ through grain boundaries and voids. As the result, as shown in
FIG. 1D
, a dopant-depleted layer
8
is formed in first silicon film pattern
3
′ near first silicide film pattern
4
′.
Next, as shown in
FIG. 1E
, a second silicon nitride film (not shown) is deposited on the upper surface of the entire structure as illustrated in FIG.
1
D. Thereafter, anisotropic etching is performed to form a sidewall spacer
5
′ at both sides of word line
20
, silicon oxide film pattern
5
′ and silicon nitride film pattern
6
′. Then, an interlayer insulator film
10
is deposited so as to completely cover word line
20
, silicon oxide film pattern
5
, silicon nitride film pattern
6
and sidewall spacer
9
.
Next, as shown in
FIG. 1F
, a photoresist film (not shown) is coated on the upper surface of the interlayer insulator film
10
. Thereafter, a second photoresist film pattern
11
is formed on insulator film
10
by exposure and developing processes. Then, using the second photoresist film pattern
11
as a mask, the interlayer insulator film
10
, the silicon nitride film pattern
6
′ and the silicon oxide film pattern
5
′ are sequentially etched to form contact hole
25
exposing the upper surface of the first silicide film pattern
4
′ and an interlayer insulator film pattern
10
′.
Next, as shown in
FIG. 1G
, the second photoresist film pattern
11
is removed. Doped second silicon film
12
and second silicide film
13
are then stacked on the upper surface of the interlayer insulator film pattern
10
′ and in contact hole
25
by sequentially depositing them.
Next, as shown in
FIG. 1H
, a bit line is formed of a second silicide film pattern
13
′ and a second silicon film pattern
12
′ by patterning the second silicide film pattern
13
and the second silicon film
12
.
In the conventional structure of a word line and a bit line using polycide thus described, the first silicide film pattern
4
′ constituting the word line and the second silicon film pattern
12
′ constituting the bit line are connected in series to contact each other. However, as described above, a dopant-depletion layer
8
is formed between the first silicon film pattern
3
′ and the first silicide film pattern
4
′. Since the dopant-depleted layer
8
is a region with a small number of carriers flowing current, it has a high resistance, resulting in the increase of the contact resistance between the word line
20
and the bit line
30
.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an integrated circuit line and method of manufacturing thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An aspect of the present invention is that low resistance contacts are provided on integrated circuit lines.
Another aspect of the present invention is that

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