Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-05-19
2004-08-10
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S610000, C438S672000, C257S770000
Reexamination Certificate
active
06774036
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to microelectronic trenched feature formation and more particularly to the formation of an interconnect from a nanocrystal solution.
BACKGROUND OF THE INVENTION
An integrated circuit requires conductive interconnects between semiconducting domains in order to communicate signals therebetween. In order to create ever faster microprocessors, smaller dimension interconnects of higher conductivity materials is an ongoing goal.
As microelectronic efficiencies have increased, interconnects have decreased in dimensional size and efforts have been made to increase the electrical conductivity of interconnect features. There is an ongoing need for ever smaller interconnects.
The rapid miniaturization of interconnects is occurring simultaneously with the transition from Al to Cu metallization for sub-0.25 &mgr;m ICs. The transition from Al to Cu has led to a change in the way interconnects are formed. While Al has been deposited as a blanket layer which is then patterned by reactive ion etching, Cu interconnects are formed by evaporative deposition into preformed (damascene) trenches and vias followed by chemical mechanical polishing (CMP).
As the interconnect width decreases and the aspect ratio increases, conventional vacuum deposition techniques approach the theoretical resolution threshold. Deep, narrow trenches and vias preferentially collect material at the damascene feature edges, leading to void formation. Blanket and selective chemical vapor deposition (CVD) are well-established Cu deposition techniques that have a demonstrated ability to fill current interconnect trenches. (A. E. Kaloyeros and M. A. Fury,
MRS Bull
. (June 1993), pp. 22-29).
Nonetheless, CVD does not inherently fill trenches preferentially over any other portion of substrate having nucleation sites. Unlike CVD, the proposed method preferentially deposits Cu into trenches based on differential solvent evaporation associated with trenches and as such is expected to work better, the narrower the trench width and higher the aspect ratio. Additionally, heating of the IC substrate during CVD to assure crystalline growth degrades fine architecture structures on the substrate. Thus, the semiconductor industry is in need of an interconnect formation process capable of achieving higher resolution at lower temperature and ideally, at a lower cost.
The mesoscopic size regime between atoms and bulk materials is characterized by unusual properties. Mesoscopic systems exhibit collective atomic behavior, but not to a sufficient extent so as to preclude quantized effects. Many of the unusual thermodynamic and spectroscopic anomalies associated with mesoscopic systems are attributable to surface effects. Studies have shown surface energies that are 10 to 400% greater for nanocrystals than for bulk Au and Pt (C. Solliard and M. Flueli,
Surf. Sci
. 156 (1985), pp. 487-494), and Al (J. Wolterdorf, A. S. Nepijko and E. Pippel,
Surf. Sci
. 106 (1981), pp. 64-72). In the bulk, surface atoms represent such a small percentage of the total that surface effects are largely inconsequential. Surfaces generally possess modified atomic coordination numbers, geometries and diminished lattice energies relative to the bulk. The result of these modifications is that physical, spectroscopic, and thermodynamic properties, which are constant in the bulk, become size dependent variables in nanocrystals. The ability to modify the thermodynamic properties of nanocrystals, particularly the melting temperature, is exploited in the present invention to produce thin film IC structures at low temperature.
Metallic nanocrystals have been shown to reduce melting temperatures compared with the bulk. (Ph. Buffat and J-P. Borel,
Phys. Rev. A
, 13 (1976), pp. 2287-2298; C. J. Coombes,
J. Phys
. 2 (1972), pp. 441-449; J. Eckert, J. C. Holzer, C. C. Ahn, Z. Fu and W. L. Johnson,
Nanostruct. Matls
. 2 (1993), pp. 407-413; C. R. M. Wronski,
Brit. J. Appl. Phys
. 18 (1967), pp. 1731-1737 and M. Wautelet,
J. Phys. D
, 24 (1991), pp. 343-346). The depression in melting and annealing temperature is evident throughout the nanocrystal size regime, with the most dramatic effects observed in nanocrystals having a diameter from 2 to 6 nm. Melting studies on a range of nanocrystals have established that the melting temperature is size dependent in the nanometer size regime and is approximately proportional to the inverse particle radius regardless of the material identity. The size dependent melting temperature of metallic nanocrystals has included studies of Au, Pb and In, Al and Sn. (Au: Ph. Buffat and J-P. Borel,
Phys. Rev. A
, 13 (1976), pp. 2287-2298; Pb and In: C. J. Coombes,
J. Phys
. 2 (1972), pp. 441-449; Al: J. Eckert, J. C. Holzer, C. C. Ahn, Z. Fu and W. L. Johnson,
Nanostruct. Matls
2 (1993), pp. 407-413; and Sn: C. R. M. Wronski,
Brit. J. Appl. Phys
. 18 (1967), pp. 1731-1737). The reduction in melting temperature as a function of nanocrystal size can be enormous. For example, 2 nm Au nanocrystals melt at about 300 degrees Celsius, as compared to 1065 degrees Celsius for bulk gold. (M. Wautelet,
J. Phys. D
, 24 (1991), pp. 343-346).
SUMMARY OF THE INVENTION
A method is described for producing a structure including the application of a solvent containing metal or semiconductor nanocrystals to a wafer having a trench cut therein. The nanocrystals having a diameter of between 1 and 20 nanometers. Heating the nanocrystals to form a continuous polycrystalline domain from the nanocrystals within the trench. The nanocrystals are applied alternatively as a coating overlying trench features, with the nanocrystal wicking into the features upon heating or by direct coating into features. The nanocrystals are preferably copper nanocrystals when the structure is destined to form an interconnect. A microelectronic structure is also formed including nanocrystalline domains in electrical contact with one another, said domains formed to an existing recess within a wafer substrate. The use of nanocrystals to form microelectronic structures in an existing recess within a wafer substrate is also taught.
DETAILED DESCRIPTION OF THE INVENTION
A method is detailed herein which uses a damascene process to create interconnects from nanocrystalline precursors materials. While the present invention is not limited to a particular metal, or metallic cation-containing compound such as an oxide, nitride, phosphide, or intermetallic, it is particularly well suited for the efficient formation of copper interconnects at temperatures below 400 degrees Celsius and even below 300 degrees Celsius. A silicon wafer that has been patterned by lithography and etched to form a series of trenches is the substrate for the instant invention the exposed surface of which also contains SiO
2
. It is appreciated that an intermediate wetting layer is optionally applied to the substrate to promote interconnect wetting thereof and to prevent interdiffusion during subsequent IC processing.
The present invention identifies significant cost efficiencies based on the deposition characteristics of nanocrystal-based construction of electronic devices. The nanocrystal solutions or suspensions are applied by spray or spin coating onto a trenched integrated circuit (IC) wafer. The present invention supplants expensive vacuum evaporation equipment with a paint booth or spin coating technology for the formation of integrated circuitry interconnect structures. Unlike chemical and physical vapor deposition techniques, the present invention selectively deposits nanocrystal particulate in the IC trenches by taking advantage of the slower volatilization of a solvent carrier from trenches, causing the nanocrystals to congregate in high aspect ratio features. As a result, the quantity of extraneous deposition material, which must be removed by CMP, is diminished. Lastly, an environmental benefit results from pre-selecting aqueous and or benign organic solvents the nanocrystal solution, in place of solvents currently used in the chip manufacturing process.
The present
Gifford, Krass, Groh Sprinkle, Anderson & Citkowski, P.C.
Picardat Kevin M.
LandOfFree
Integrated circuit trenched features and method of producing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit trenched features and method of producing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit trenched features and method of producing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3323363