Integrated circuit transistor having drain junction offset

Details Integrated circuit transistor having drain junction offset Integrated circuit transistor having drain junction offset

1995-09-05

1998-03-17

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257346, 257408, 257387, H01L 2976

Patent

active

057290369

ABSTRACT:
A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode. Due to the difference in diffusion rates between the relatively slow-diffusing dopant and the relatively fast-diffusing dopant, a transistor having a drain junction offset is formed.

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Sergio Bampi, et al., "A Modified Lightly Doped Drain Structure for VLSI MOSFET's", pp. 1769-1779, IEEE Transactions on Electron Devices, vol. ED-33. No. 11, Nov. 1986.

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