Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-05-25
2001-04-03
Mai, Son (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000
Reexamination Certificate
active
06211697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to gate arrays, and more particularly, to an integrated circuit that includes both a field-programmable gate array and a mask metal programmable (or “hard”) gate array having the same underlying structure.
2. Description of the Related Art
A field-programmable gate array (FPGA) is an integrated circuit (IC) that includes a two-dimensional array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. The cells are linked to one another by programmable buses. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing all Boolean functions of a few variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain one or two flip-flops. Two types of logic cells found in FPGAs are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture.
FPGAs typically include a physical template that includes an array of circuits, sets of uncommitted routing interconnects, and sets of user programmable switches associated with both the circuits and the routing interconnects. When these switches are properly programmed (set to on or off states), the template or the underlying circuit and interconnect of the FPGA is customized or configured to perform specific customized functions. By reprogramming the on-off states of these switches, an FPGA can perform many different functions. Once a specific configuration of an FPGA has been decided upon, it can be configured to perform that one specific function.
The user programmable switches in an FPGA can be implemented in various technologies, such as ONO antifuse, M-M antifuse, SRAM memory cell, Flash EPROM memory cell, and EEPROM memory cell. FPGAs that employ fuses or antifuses as switches can be programmed only once. A memory cell controlled switch implementation of an FPGA can be reprogrammed repeatedly. In this scenario, an NMOS transistor is typically used as the switch to either connect or disconnect two selected points (A, B) in the circuit. The NMOS' source and drain nodes are connected to points A, B respectively, and its gate node is directly or indirectly connected to the memory cell. By setting the state of the memory cell to either logical “1” or “0”, the switch can be turned on or off and thus point A and B are either connected or disconnected. Thus, the ability to program these switches provides for a very flexible device.
FPGAs can store the program that determines the circuit to be implemented in a RAM or PROM on the FPGA chip. The pattern of the data in this configuration memory CM determines the cells' functions and their interconnection wiring. Each bit of CM controls a transistor switch in the target circuit that can select some cell function or make (or break) some connection. By replacing the contents of CM, designers can make design changes or correct design errors. The CM can be downloaded from an external source or stored on-chip. This type of FPGA can be reprogrammed repeatedly, which significantly reduces development and manufacturing costs.
In general, an FPGA is one type of programmable logic device (PLD), i.e., a device that contains many gates or other general-purpose cells whose interconnections can be configured or “programmed” to implement any desired combinational or sequential function. As its name implies, an FPGA is “field-programmable”, meaning that the device is generally programmed by designers or end users “in the field” via small, low-cost programming units. This is in contrast to mask programmable devices which require special steps in the IC chip-manufacturing process. A field-programming unit typically uses design software to program the FPGA. The design software translates a specific configuration of the programmable switches desired by the end-user into a bit stream which is fed into the FPGA. The bit stream creates the pattern of the data in the configuration memory CM that determines whether each memory cell stores a “1” or a “0”. The stored bit in each CM controls whether its associated transistor switch is turned on or off.
Designers of FPGAs (as well as other PLDs) often provide their circuit designs to IC manufacturers who embed the FPGA designs into larger ICs. An example of such a larger IC is a system on a chip (SOC) that includes the embedded FPGA as well as several other components. The several other components may include, for example, a microprocessor, memory, arithmetic logic unit (ALU), state machine, etc. In this scenario the embedded FPGA may be only a small part of the whole SOC.
When an FPGA that has been programmed to perform one specific function is compared to an application specific integrated circuit (ASIC) that has been designed and manufactured to perform that same specific function, the FPGA will necessarily be a larger device than the ASIC. This is because FPGAs are very flexible devices that are capable of implementing many different functions, and as such, they include a large amount of excess circuitry that is either not used or could be replaced with hard-wired connections when performing one specific function. Such excess circuitry generally includes the numerous programmable transistor switches and corresponding memory cells that are not used in implementing the one specific function, the memory cells inside of functional groups, and the FPGA programming circuitry. This excess circuitry is typically eliminated in the design of an ASIC which makes the ASIC a smaller device. An ASIC, on the other hand, is not a flexible device. In other words, once an ASIC has been designed and manufactured it cannot be reconfigured to perform a different function like the FPGA can.
Similar to an ASIC, a “hard” gate array (GA), i.e., a non-programmable GA, can be designed to perform a specific function. Such a GA will also be smaller than an FPGA that has been programmed to perform that same specific function due to the elimination of excess circuitry. Furthermore, a GA is more likely to be a faster device and less power consuming than an FPGA. This is because many of the circuit connections within the FPGA are provided by transistors, whereas circuit connections in the GA are hard-wired connections. The transistor connections, even when the transistors are turned on, provides more resistance than a hard-wired connection. This results in slower speed with greater power consumption.
As mentioned above, FPGAs are typically programmed with design software that compiles a specific user design into FPGA configuration data. The design software assembles the configuration data into a bit stream, i.e., a stream of ones and zeros, that is used to program the configuration memories for the programmable switches in the FPGA. Design software may also be used to program hard GAs. In the hard GA scenario, instead of generating a bit stream, the design software generates data indicating where metal connections are to be made in the GA.
End users typically use design software to test different designs and run simulations for FPGAs and GAs. Separate design software packages, however, have heretofore been used for FPGAs and GAs. In other words, one design software package is used for programming FPGAs, and a different design software package is used for designing hard GAs. The requirement for different design software packages is cumbersome, particularly in the scenario where the FPGA and the GA are embedded in the same IC. This is because in order to model or simulate the FPGA and the hard GA working together, the designer must manually combine the results of the diffe
Feng Sheng
Huang Eddy Chieh
Lien Jung-Cheun
Sun Chung-yuan
Actel
Mai Son
McCutchen Doyle Brown & Enersen LLP
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