Integrated circuit test structure and test process

Details Integrated circuit test structure and test process Integrated circuit test structure and test process

1991-09-06

1999-04-27

Aftergut, Jeff H.

Adhesive bonding and miscellaneous chemical manufacture

Methods

Surface bonding and/or assembly therefor

156247, 174 524, B32B 3200

Patent

active

058977287

ABSTRACT:
For fully testing and burning-in an integrated circuit chip before it is incorporated into a high density interconnect or other standard hybrid bare chip circuit, a temporary test substrate having pins extending therethrough holds the chip within a cavity. Chip pads are electrically connected with the pins to create a package that can be tested using commercially available testing and burn-in devices. After testing, the chip is retrieved from the test structure undamaged. In using HDI techniques to interconnect the chip with the pins, metal-filled vias in a polymer layer overlying the temporary test substrate electrically connect the chip to the pins through a metal interconnect pattern on the polymer layer. In another embodiment, the chip is interconnected with the pins through wire bonds. Metal-filled vias pass through an insulative coating on the chip and make electrical contact with the chip pad. A temporary buffer pad connected to a respective via and offset from the chip pad connected to that via comprises a wire-bonding site.

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Bry, A., et. al. IBM Technical Disclosure Bulletin, "Reusable Chip Test Package", vol. 22, No. 4, Sep. 1979, pp. 1476-1477.

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