Integrated circuit system employing dipole multiple exposure

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C430S311000, C430S394000, C430S396000, C250S492200

Reexamination Certificate

active

07926000

ABSTRACT:
An integrated circuit system that includes: providing a first mask including a first feature; exposing the first mask to a radiation source to form an image of the first feature on a photoresist material that is larger than a structure to be formed, the photoresist material being formed over a substrate that includes the integrated circuit system; providing a second mask including a second feature; aligning the second mask over the image of the first mask to form an overlap region; and exposing the second mask to the radiation source to form an image of the second feature on the photoresist material that is larger than the structure to be formed.

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patent: 2003/0085360 (2003-05-01), Parker et al.
patent: 2004/0021845 (2004-02-01), Kawahara
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patent: 2005/0005257 (2005-01-01), Eurlings et al.
patent: 2005/0221233 (2005-10-01), Minvielle et al.
patent: 2006/0240331 (2006-10-01), O'Brien et al.
patent: 2009/0212213 (2009-08-01), Nakasuji et al.

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