Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-19
2003-01-14
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S788000, C438S714000, C438S765000
Reexamination Certificate
active
06506678
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
The subject matter of this application relates to the subject matter of the copending application entitled “INTERCONNECTION SYSTEM WITH LATERAL BARRIER LAYER”, assigned to the assignee of this application, and filed on the same date as this application.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to integrated circuit structures having low k porous aluminum oxide dielectric material formed between aluminum metal line structures.
2. Description of the Related Art
In the construction of integrated circuit structures, dielectric materials such as silicon oxide (SiO
2
) have been conventionally used to electrically separate and isolate or insulate conductive elements of the integrated circuit structure from one another. However, as the spacings between such conductive elements in the integrated circuit structure have become smaller and smaller, the capacitance between such conductive elements through the silicon oxide dielectric has become of increasing concern. Such capacitance has a negative influence on the overall performance of the integrated circuit structure in a number of ways, including its effect on speed of the circuitry and cross-coupling (crosstalk) between adjacent conductive elements.
Because of this ever increasing problem of capacitance between adjacent conductive elements separated by conventional silicon oxide (SiO
2
) insulation, as the scale of integrated circuit structures continues to reduce, the use of other insulation materials having lower dielectric constants than conventional silicon oxide has been proposed. These include the substitution of organic polymer dielectric material, the use of altered silicon oxide such as porous or fluorinated silicon oxide, and silicon oxide having incorporated hydrogen or hydrocarbon groups. Formation or deposition of these low k dielectric materials on a surface of an integrated circuit structure is generally carried using either a spin-on technology or chemical vapor deposition (CVD)—either thermal or plasma enhanced CVD (PECVD). Low k materials, such as polymers or porous silicon oxide, deposited by spin-on technology, usually exhibit a high level of internal stress that causes reliability problems. Materials deposited by CVD techniques, such as hydrocarbon-modified silicon oxide, are characterized by strong adhesion, but in some cases gap filling issues can arise, especially when using PECVD technology to form the desired film.
Dobson et al., in an article entitled “Advanced SiO
2
Planarization Using Silane and H
2
O
2
”, published in Semiconductor International, December 1994, at pages 85-88, describe the low temperature formation of SiO
2
by reaction of silane (SiH
4
) with hydrogen peroxide (H
2
O
2
) to produce a silicon oxide which flows like a liquid and thus exhibits good gap fill characteristics.
In an article by L. Peters, entitled “Pursuing the Perfect Low-K Dielectric”, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a Flowfill chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The process is said to react methyl silane (CH
3
—SiH
3
) with hydrogen peroxide (H
2
O
2
) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is then annealed to remove moisture. Such carbon-containing silicon oxide insulating materials formed in this manner, sometimes referred to as low k carbon-doped silicon oxide dielectric material, exhibit good gap-filling capabilities and at the same time are characterized by a dielectric constant less than 3.0 and remain stable during subsequent annealing at temperatures of up to 500° C.
An article by S. McClatchie et al. entitled “Low Dielectric Constant Oxide Films Deposited Using CVD Techniques”, published in the 1998 Proceedings of the Fourth International Dielectrics For ULSI Multilevel Interconnection Conference (Dumic) held on Feb. 16-17, 1998 at Santa Clara, Calif., at pages 311-318, also describes the formation of methyl-doped silicon oxide by the low-k Flowfill process of reacting methyl silane with H
2
O
2
to achieve a dielectric constant of ~2.9.
The low dielectric constant (k) value of these types of materials is achieved by the incorporation of C—H containing groups into the SiO
2
-based matrices. The larger the carbon concentration becomes in the SiO
2
polymer matrices, the lower the expected value of k. However, one of the major problems associated with this type of low k material is its poor oxidation resistance. Hydrocarbon groups introduced into the bulk of these materials can be easily damaged or destroyed by oxidizing agents during subsequent etching, chemical/mechanical polishing (C/MP), and photoresist stripping (ashing) processes.
It would, therefore, be desirable to provide an integrated circuit structure with at least one layer of low k material which combines the very low k and chemical inert characteristics of porous silicon oxide with the adhesion and low level of internal stress of CVD-based low k material, as well as good gap fill characteristics.
Lazarouk et al., in an article entitled “Anisotropy of Aluminum Porous Anodization Process for VLSI Planar Metallization”, published at pages 651-6 of Advanced Metallization for Devices and Circuits—Science in 1994, describe the anodization of a masked aluminum layer to form metal interconnects as a substitute for etching of the masked aluminum layer, and the use of anodizing voltage as a control of the anisotropic versus isotropic anodization of the aluminum layer.
SUMMARY OF THE INVENTION
The invention comprises an integrated circuit structure having aluminum lines formed thereon which are at least horizontally separated from one another by low k porous aluminum oxide dielectric material formed by anodization of aluminum. In a first embodiment, an aluminum layer is formed over the integrated circuit structure and the aluminum layer is then patterned to form a plurality of aluminum metal lines or interconnects. The patterned aluminum metal lines are then anodized by contacting the exposed surfaces of the patterned aluminum metal lines with an anodizing material, such as an acid anodizing bath, while applying a positive anodizing voltage to the patterned aluminum metal to form anodized aluminum oxide on the exposed upper and sidewall surfaces of the patterned aluminum in contact with the anodizing material. Depending upon the spacing between adjacent aluminum metal lines and the initial thickness of the aluminum metal lines prior to anodization, the anodization may be carried out until the anodized aluminum films on horizontally adjacent aluminum metal lines contact one another, or may be stopped prior to this point, leaving a gap between the anodized aluminum oxide films on adjacent aluminum metal lines. This gap, depending upon its width, may then be either filled with other low k dielectric material or by standard (non-low k) dielectric material such as conventional silicon oxide (SiO
2
). Finally, a capping layer of non-porous dielectric material, such as conventional silicon oxide (SiO
2
), which may comprise the material formed in the gap between horizontally adjacent aluminum oxide films on aluminum lines, is formed over the porous anodized aluminum oxide to seal the surface of the porous aluminum oxide.
In a preferred modification of this embodiment, one or more electrically conductive layers are first formed over the integrated circuit structure respectively to facilitate adherence of the aluminum to underlying portions of the integrated circuit structure and to prevent interaction between aluminum and silicon in the underlying integrated circuit structure. Then an antireflective lay
LSI Logic Corporation
Rocchegiani Renzo N.
Smith Matthew
Taylor John P.
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