Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1997-08-18
2001-07-17
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S530000, C257S537000, C438S004000, C438S384000, C338S114000, C338S140000, C338S195000, C338S319000, C338S320000
Reexamination Certificate
active
06262434
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the manufacture of integrated circuits (IC's). More particularly, the present invention relates to new integrated circuit (IC) structures, and methods therefor, that permit individual devices of the IC to be accurately measured while minimizing the IC's overall manufacturing complexity and cost.
Integrated circuits (IC's) and manufacturing techniques therefor are well known in the art. An IC comprises generally of a circuit or groups of circuits, each of which are formed of interconnected devices fabricated on a semiconductor substrate. Typically, the devices are fabricated in batch, i.e., similar devices are formed together in one or more conventional semiconductor processing steps. Once fabricated on the semiconductor die, the circuit(s) may then be bonded to a leadframe, whose pins provide terminals for inputs, outputs, Vcc, ground, and the like.
In some applications, the accuracy of each individual device of the circuit is of paramount importance. Such circuits are precise in nature and require their constituent devices to be within narrowly defined tolerance limits. By way of example, the resistance values of individual resistors in a resistor-divider network need to be tightly controlled in order for the resistor-divider network to provide a reasonably accurate voltage ratio.
To facilitate discussion, FIG. I illustrates a plurality of thin film resistor networks known as Thevenin Equivalent Terminator circuits. Each resistor network is formed of interconnected devices representative of the type that may be fabricated using a conventional semiconductor processing technique. Although only three thin film resistor networks
102
,
104
, and
106
are shown in
FIG. 1
, a Thevenin Equivalent Terminator IC may contain any number of interconnected resistor networks, e.g.,
12
,
18
, or even more depending on needs. It should also be borne in mind that although resistor networks are employed herein to simplify the illustration, the inventive concept is not limited to these types of IC's and applies equally well to other types of IC's that require accurate measurements of its constituent devices.
Within resistor network
102
, thin-film resistors
108
and
110
are shown coupled in series between Vcc and ground. At the junction of resistors
108
and
110
, an input terminal
112
is defined. As is apparent, resistor network
102
forms a resistor-divider circuit to provide a voltage ratio of supply voltage Vcc at input terminal
112
. Resistor network
102
may be employed as, for example, a precise equivalent termination resistor for a bus that couples to input terminal
112
.
In order to ensure the accuracy of resistor network
102
, the resistance values of individual resistors
108
and
110
need to be tightly controlled. If the fabrication process is highly accurate, individual resistors
108
and
110
would be fabricated to their specified resistance values, rendering any post-fabrication adjustment of their resistance values unnecessary. For some precise thin-film resistor networks, however, it has been found that contemporary IC fabrication techniques do not have the degree of accuracy necessary to produce resistors with sufficiently precise resistance values. Consequently, the fabrication steps are employed to produce thin-film resistors having roughly the specified resistance values. Post-fabrication processing steps are subsequently performed on the fabricated resistors to bring them within the required tolerance limit.
To obtain the required degree of accuracy, each individual resistor in the Thevenin Equivalent Terminator of
FIG. 1
may be fabricated to a lower resistance value than is intended in the final circuit, e.g., the cross-section area of each resistor's resistive portion is fabricated to be slightly larger than required for its intended resistance value. As part of the fabrication process, the resistors are connected together to form the desired resistive networks, complete with bonding pads to connect the resistive network to the appropriate pins of the IC package.
During wafer testing of the die, the value of each resistor is then measured in an appropriately designed testing apparatus. Depending on the measured value, a laser trimming apparatus is employed to trim away an appropriate amount of resistive material from the measured resistor body to reduce the resistor body's cross-sectional area, thereby bringing its resistance value within the specified tolerance limit. The testing and trimming operations are typically performed for each resistor in order to ensure the precision of the resulting resistor network.
In the prior art, the measuring and trimming operations are performed during wafer sort, i.e., after the individual resistors have been interconnected into the resistor networks. After the individual resistors are interconnected to other resistors in final circuit form, however, it is difficult to accurately measure the resistance value of each individual resistor. For example, if measurement probes are placed at input terminal
112
and ground node
114
to measure the resistance value of resistor
110
, a sneak path of current through resistor
108
(and through other resistors of the interconnected resistor networks of
FIG. 1
) will render that measurement inaccurate. Further, since other resistors of
FIG. 1
are also fabricated by the same fabrication process that produces resistor
110
, they also suffer from fabrication-related inaccuracies. As such, it is not possible to rely on their specified values to compute the actual resistance of resistor
110
when a measurement is taken across input terminal
112
and ground node
114
. Since the resistance value of resistor
110
cannot be accurately measured after fabrication, it is not possible then to accurately ascertain the extent to which resistor
110
needs to be laser-trimmed in order to bring it within the specified tolerance.
One potential solution involves laying out and fabricating the devices of an IC such that they remain electrically disconnected from one another after the fabrication steps. Thereafter, measurement may be made and any necessary adjustment may be performed on each device. Once the devices are properly adjusted and brought within the required tolerance limit, a bonding wire may be employed to provide an electrical path to each individual device, thereby forming the desired circuit. If a circuit requires two thin-film resistors, for example resistor network
102
of
FIG. 1
, resistors
108
and
110
may be fabricated so that they form two individual, electrically disconnected devices after fabrication. After measurement and adjustment are performed, two bonding wires, i.e., one for each device, may be then employed to couple the ends of resistors
108
and
110
to input terminal
112
.
While the above-discussed potential solution renders the accurate measurement of each device possible, there are drawbacks. For example, when multiple bonding wires and corresponding bonding steps are employed to interconnect the individual devices together into the final circuit, manufacturing complexities and costs increase. For circuits having a large number of interconnected devices, the additional number of bonding wires and bonding steps required to electrically couple all the individual devices together may render the resulting IC prohibitively difficult to layout and/or manufacture.
In view of the foregoing, improved integrated circuit structures and methods therefor are desired. In particular, it is desirable to form an improved integrated circuit structure that permits the individual devices to be accurately measured after fabrication while also permitting the devices to be efficiently assembled into the final circuit after measurements (and any necessary adjustments) are performed.
SUMMARY OF THE INVENTION
The present invention relates, in one embodiment, to an integrated circuit including a first circuit structure, a first conductive bonding pad coupled to
Beyer Weaver & Thomas LLP
California Micro Devices Corporation
Ngo Ngan V.
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