Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2000-02-10
2002-07-30
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S508000, C257S701000
Reexamination Certificate
active
06426545
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to packaging integrated circuits, and more particularly, to structures and methods for absorbing stress between a first electrical structure and a second electrical structure connected together, wherein the first and second structures have different coefficients of thermal expansion.
BACKGROUND OF THE INVENTION
Typical dielectric materials employed in electronic packaging, and printed circuit processes, have a Young's modulus in the range of 200,000 to 2,000,000 psi. When such materials are used with ball grid array (BGA) packages which have large solder balls, the resultant stresses on the solder ball interconnections are acceptable and large numbers of thermal cycles can be endured.
As the size of these packages being interconnected is reduced, for example, to the same or nearly the same size as the packaged integrated circuit chip itself, the size of the solder balls that are used must also be reduced. Also, certain structures use small solid metal bumps on packaging, and depend on solder stenciled on lands of, for example, the printed circuit board for connection. The use of small solid balls or solder bumps increases the strain that the solder interconnect and the balls or bumps must endure during thermal cycling. This increased strain leads to fatigue and premature failure of the connection. Solder has a characteristic where fatigue occurs in less than 100 cycles at a five percent strain, whereas more than one thousand cycles can be obtained before fatigue if the strain is maintained at or below one percent.
Thus, presented herein is a novel low modulus high elongation dielectric material which when employed in the structures and methods described below maintains the strain on the solder interconnect and interconnection bumps to a minimum desired level.
DISCLOSURE OF THE INVENTION
Typical electronic assemblies have been analyzed by stress/strain analysis. It has been found that for coatings in the 20-60 micron thickness-range a modulus below 20,000 psi allows the dielectric material to take up expected strain without exceeding levels of strain that would fatigue the interconnection bumps. This is true regardless of the thickness of the solder or solid interconnect. Further, if the dielectric material has a strain limit (i.e., ultimate-elongation property) of greater than twenty percent, then the dielectric material will not fail and a highly reliable system is obtained.
In addition to low modulus and high strain (elongation) capability, several other features of the material are also preferred for the material to be useful as a dielectric in electronic packages and in printed circuit additive layer applications.
First, it is desirable to pattern small via holes in the material, e.g., by photo patterning such that when the material is exposed to UV light through a mask and then developed, the desired via holes are formed. Ideally the via holes to be formed have a hole-wall profile that is slightly smaller at the base than at the top. This provides for easier metallization thereof. Many photo patternable materials are limited to a maximum thickness of under 20 microns. This is due to the natural absorption of the UV light by the material itself. Photo-patternable polyimide is one example. To take maximum advantage of the elongation of the material, however, it is believed preferable to process at a thickness the same or greater than the maximum displacement to be encountered. As an example, typical printed circuit board expansion is 20 ppm/degree C. The operational temperature-range is 100 C. and a maximum package size is 1 inch.
This gives a maximum displacement of
100C*20E−06*1 inch/2=0.001 inch.
From this it can be seen that the thickness of the dielectric should be at least 1 mil (25 micron) and ideally the thickness should be greater than this value. A thickness range of 25 to 60 microns is believed to cover most requirements.
The adhesion properties of the material are also significant. It must adhere well throughout processing and through significant environmental stresses. The material must adhere to silicon and gallium arsenide of typical IC chips. Further, it must adhere to copper, printed circuit material and to itself for multi-layer circuits.
Additionally, processing temperatures required for the material should be less than 200 C because printed circuit boards will warp above this temperature. Where chips first structures are involved possible damage to sensitive IC chips can occur on prolonged exposure above 200 C. Finally, the material should be capable of accepting metallization. Specifically, in the printed circuit and low cost packaging industry the preferred method of metallization is electroless copper deposition, wherein the dielectric is adhesion promoted, catalyzed and then electroless copper deposited from commercially available electroless copper baths. For the dielectric to be useful it is desirable that the electroless copper have a peel strength in the 3 to 4 lb./inch range.
It should be noted that materials are available which have some but not all of the properties noted above for use as a low modulus high elongation packaging or additive printed circuit dielectric in accordance with the present invention.
In view of the above, one object of this invention is to provide a dielectric material that has a modulus below, e.g., 50,000 psi and a strain capability which exceeds twenty percent.
Another object of the invention is to provide a dielectric material which can be patterned to form small via holes (with diameters less than 2× thickness) using conventional photo exposure and development techniques in sections which are 20-60 microns thick.
A further object of the invention is to provide a dielectric material which when developed results in a hole-wall profile which is positive rather than negative.
Another object of the invention is to provide a dielectric material that can be coated with electroless copper using commercially available baths with adhesion peel strengths in excess of 3 lb./inch.
A still further object of the invention is to provide a material system that can be coated with sputtered metallization using titanium or chrome followed by copper metallization with good adhesion peel strengths and with ability to remove seed layers without damage to the material.
Still another object of the invention is to provide a material system which has good adhesion from the dielectric to silicon IC chips, copper, printed circuit board material, and lower layers of the same dielectric.
Yet another object of the invention is to be able to use the low modulus material disclosed herein to provide a metal/dielectric structure that will absorb differential expansion between two electrical structures, such as a printed circuit board and an associated IC in a module, such that the solder interconnect is not fatigued on thermal cycling.
Briefly summarized therefore, this invention comprises in one aspect a structure for absorbing stress between a first electrical structure and a second electrical structure. This structure includes a dielectric material disposed on at least one of the first electrical structure and the second electrical structure. The dielectric material is a low modulus material which has a high ultimate elongation property, such that the dielectric material comprises a low modulus high elongation (LMHE) dielectric which functions to absorb stress between the first and second electrical structures resulting from the first and second electrical structures having different coefficients of thermal expansion.
In another aspect, a method for absorbing stress between a first electrical structure and a second electrical structure is provided. The method includes: providing a dielectric material disposed over at least one of the first electrical structure and the second electrical structure; and wherein the providing of the dielectric material includes providing a low modulus material which has a high ultimate elongation property such that the dielectric materia
Eichelberger Charles W.
Kohl James E.
EPIC Technologies, Inc.
Heslin Rothenberg Farley & & Mesiti P.C.
Pizarro-Crespo Marcos D.
Radigan, Esq. Kevin P.
Weiss Howard
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