Integrated circuit structure with dual thickness cobalt silicide

Details Integrated circuit structure with dual thickness cobalt silicide Integrated circuit structure with dual thickness cobalt silicide

1999-06-15

2000-08-15

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438655, 438682, H01L 214763, H01L 2144

Patent

active

061036102

ABSTRACT:
A process for the controlled formation of dual thickness cobalt silicide layers on predetermined regions during the manufacturing of an integrated circuit that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, an integrated circuit (IC) structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A cobalt layer is then deposited over the IC structure, followed by the deposition of a titanium capping layer on the cobalt layer. The titanium capping layer is then pattered above predetermined regions of the IC structure. Cobalt in the cobalt layer that is in direct contact with silicon in the exposed silicon surfaces is subsequently reacted to form relatively thick cobalt silicide layers on the predetermined regions and relatively thin cobalt silicide layers elsewhere. The present invention also provides an IC structure with dual thickness cobalt silicide layers. The IC structure includes pluralities of first and second MOS transistor structures having source regions, drain regions and polysilicon gates. Relatively thin cobalt silicide layers are disposed on the first MOS transistor structures with shallow source and drain regions, while relatively thick cobalt silicide layers are disposed on the second MOS transistor structures with deep source and drain regions.

REFERENCES:
patent: 4877755 (1989-10-01), Rodder
patent: 5034348 (1991-07-01), Hartswick et al.
patent: 5736461 (1998-04-01), Berti et al.
patent: 6040606 (2000-03-01), Blair
Antonio C. Berti, et al., A Manufacturable Process for the Formation of Self Aligned Cobalt Silicide in a Sub Micrometer CMOS Technology, VMIC Conference, Jun. 9-10, 1992, pp. 267-273.
Karen Maex, et al., Self-Aligned Silicides for ULSI, Material Research Society Symposium Proceedings, vol. 260, Apr. 27-May 1, 1992, San Francisco, CA, pp. 133-144.
Stanley Wolf, et al., Silicon Processing for the VLSI Era--vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, 1986, pp. 388-399, No month.

Affiliated with

Also associated with

Rating

Integrated circuit structure with dual thickness cobalt silicide does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit structure with dual thickness cobalt silicide, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit structure with dual thickness cobalt silicide will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2006297