Integrated circuit structure with dual thickness cobalt silicide

Details Integrated circuit structure with dual thickness cobalt silicide Integrated circuit structure with dual thickness cobalt silicide

1998-11-04

2000-03-21

Munson, Gene M.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257413, H01L 2978, H01L 27085, H01L 2945

Patent

active

060406062

ABSTRACT:
A process for the controlled formation of dual thickness cobalt silicide layers on predetermined regions during the manufacturing of an integrated circuit that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, an integrated circuit (IC) structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A cobalt layer is then deposited over the IC structure, followed by the deposition of a titanium capping layer on the cobalt layer. The titanium capping layer is then pattered above predetermined regions of the IC structure. Cobalt in the cobalt layer that is in direct contact with silicon in the exposed silicon surfaces is subsequently reacted to form relatively thick cobalt silicide layers on the predetermined regions and relatively thin cobalt silicide layers elsewhere. The present invention also provides an IC structure with dual thickness cobalt silicide layers. The IC structure includes pluralities of first and second MOS transistor structures having source regions, drain regions and polysilicon gates. Relatively thin cobalt silicide layers are disposed on the first MOS transistor structures with shallow source and drain regions, while relatively thick cobalt silicide layers are disposed on the second MOS transistor structures with deep source and drain regions.

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Antonio C. Berti, et al., A Manufacturable Process for the Formation Of Self Aligned Cobalt Silicide in a Sub Micrometer CMOS Technology, VMIC Conference, Jun. 9-10, 1992, pp. 267-273.
Karen Maex, et al., Self-Aligned Silicides for ULSI, Material Research Society Symposium Proceedings, vol. 260, Apr. 27 -May 1, 1992, San Francisco, CA, pp. 133-144.
Stanley Wolf, et al., Silicon Processing for the VLSI ERA, Lattice Press, Sunset Beach, CA, 1986, pp. 388-399.

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