Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2007-03-06
2007-03-06
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S038000
Reexamination Certificate
active
11065793
ABSTRACT:
A storage element (10) includes a first latch (12) and a second latch (14). The first latch (12) is coupled to a first power supply voltage terminal for receiving a first power supply voltage. The second latch (14) is coupled to a second power supply voltage terminal. The second power supply voltage terminal for receiving a second power supply voltage that is lower than the first power supply voltage. During a normal mode of operation, the second power supply voltage is not provided to the second latch. During a low power mode of operation data is transferred from the first latch to the second latch and the first latch is powered down. The data is retained by the second latch while in low power mode.
REFERENCES:
patent: 6313695 (2001-11-01), Ooishi et al.
patent: 6597620 (2003-07-01), McMinn
patent: 6635934 (2003-10-01), Hidaka
patent: 6724648 (2004-04-01), Khellah et al.
patent: 7061299 (2006-06-01), Khan et al.
patent: 2001/0020858 (2001-09-01), Iwaki et al.
patent: 2003/0188241 (2003-10-01), Zyuban et al.
patent: 2004/0008071 (2004-01-01), Ko et al.
patent: 2004/0061135 (2004-04-01), Ikeno et al.
patent: 2004/0075478 (2004-04-01), Correale, Jr. et al.
patent: 2004/0143769 (2004-07-01), Deng et al.
patent: 2004/0178493 (2004-09-01), Correale, Jr.
patent: 2005/0212560 (2005-09-01), Hidaka
Correale, Jr., Anthony; “Watts” the Matter: Power Reduction Issues; IEEE; 2001; p. 9; #0-7803-7024-4/01; IEEE, USA, no month.
Lackey, David E. et al.; “Managing Power and Performance for Systems-on-Chip Designs using Voltage Islands”; IEEE; 2002; pp. 195-202; #0-7803-7607-2/02; IEEE, USA, no month.
Zyuban, Victor et al.; “Low Power Integrated Scan-Retention Mechanism”; ISLPED '02, Monterey, CA; Aug. 12-14, 2002; pp. 98-102; ACM; #1-58113-475-04/02/0008; ACM, USA.
Carballo, Juan-Antonio et al.; “A Semi-Custom Voltage-Island Technique and Its Application to High-Speed Serial Links”; ISLPED '03 Seoul, Korea; Aug. 25-27, 2003; pp. 60-65; #1-58113-682-X/03/0008; ACM; USA.
Bearden David R.
Piejko Arthur R.
Ramaraju Ravindraraj
Freescale Semiconductor Inc.
Hill Daniel D.
Le Don
LandOfFree
Integrated circuit storage element having low power data... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit storage element having low power data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit storage element having low power data... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3772716